參數(shù)資料
型號(hào): MAX9321ESA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Differential LVPECL/LVECL/HSTL Receiver/Drivers
中文描述: LINE TRANSCEIVER, PDSO8
封裝: 0.150 INCH, EXPOSED PAD, SOIC-8
文件頁數(shù): 4/9頁
文件大?。?/td> 178K
代理商: MAX9321ESA
M
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
- V
EE
= +2.25V to +3.8V, outputs loaded with 50
±1% to V
CC
- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to the smaller of 3V or V
CC
- V
EE
. Typical
values are at V
CC
- V
EE
= 3.3V, V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Notes 8, 11)
-40
°
C
TYP
+25
°
C
TYP
+85
°
C
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Added
Deterministic
Jitter (Note 10)
t
DJ
3.0Gbps
2
23
-1 PRBS pattern
57
80
57
80
57
80
ps
(p-p)
V
OH
- V
OL
300mV,
Clock pattern,
Figure 2
3.0
3.0
3.0
Switching
Frequency
f
MAX
V
OH
- V
OL
550mV,
Clock pattern,
Figure 2
2.0
2.0
2.0
GHz
Output Rise/
Fall Time
(20% to 80%)
t
R
, t
F
Figure 2
50
88
120
50
89
120
50
90
120
ps
Note 1:
Guaranteed by design and characterization.
Note 2:
Measurements are made with the device in thermal equilibrium.
Note 3:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4:
DC parameters production tested at T
A
= +25
°
C. Guaranteed by design and characterization over the full operating temp-
erature range.
Note 5:
Single-ended input operation is limited to V
CC
- V
EE
3.0V.
Note 6:
Use V
BB
as a reference for inputs on the same device only.
Note 7:
All pins open except V
CC
and V
EE
.
Note 8:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 9:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10:
Device jitter added to the input signal.
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