M
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
8
_______________________________________________________________________________________
When using the V
BB
reference output, bypass it with a
0.01μF ceramic capacitor to V
CC
. If the V
BB
reference
is not used, it can be left open. The V
BB
reference can
source or sink 0.5mA. Use V
BB
only for an input on the
same device as the V
BB
reference.
The maximum magnitude of the differential input from D
to
D
is 3.0V or V
CC
- V
EE
, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 60k
pullup to V
CC
and a 100k
pulldown to V
EE
. The noninverting input is
biased with a 100k
pulldown to V
EE
.
Specifications for the high and low voltage of the differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously (V
ILD
cannot
be higher than V
IHD
).
Outputs
Output levels are referenced to V
CC
and are consid-
ered LVPECL or LVECL, depending on the level of the
V
CC
supply. With V
CC
connected to a positive supply
and V
EE
connected to GND, the output is LVPECL. The
output is LVECL when V
CC
is connected to GND and
V
EE
is connected to a negative supply.
A single-ended input of at least V
BB
±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the V
OH
and V
OL
levels specified in the
DC Electrical
Characteristics
table.
Applications Information
Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1μF and 0.01μF capacitors in parallel as
close to the device as possible, with the 0.01μF value
capacitor closest to the device. Use multiple parallel
vias for low inductance. When using the V
BB
reference
output, bypass it with a 0.01μF ceramic capacitor to
V
CC
(if the V
BB
reference is not used, it can be left
open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9321/MAX9321A. Connect each sig-
nal of a differential input or output to a 50
characteristic impedance trace. Minimize the number of
vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50
characteristic
impedance through connectors and across cables.
Reduce skew within a differential pair by matching the
electrical length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis-
tance is the same as the regular SO package. The EP is
connected to the chip V
EE
supply. Be sure that the pad
does not touch signal lines or other supplies.
Contact Maxim's Packaging department for guidelines
on the use of EP packages.
Output Termination
Terminate outputs through 50
to V
CC
- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from the differential output, terminate
both outputs. For example, when Q is used as a single-
ended output, terminate both Q and
Q
.
Chip Information
TRANSISTOR COUNT: 162
6
SOT23
D
V
CC
1
2
3
4
8
5
7
V
EE
MAX9321A
60k
100k
100k
V
CC
V
EE
6
μ
MAX/SO
1
2
3
4
8
5
7
MAX9321A
D
N.C.
V
BB
Q
Q
60k
100k
100k
V
CC
Q
V
EE
V
CC
N.C.
V
BB
D
Q
D
Pin Configurations (continued)