參數(shù)資料
型號(hào)： MAX9317ETJ
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
中文描述： LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC32
封裝： 5 X 5 MM, 0.80 MM HEIGHT, THIN, QFN-32
文件頁數(shù)： 7/10頁
文件大?。?/td> 315K
代理商： MAX9317ETJ
respective input with a differential 100
termination to
receive LVDS signals (Figure 2(b)).
The MAX9317/MAX9317B accept LVPECL if the inputs
are externally terminated with 50
resistors from CLKA
and
CLKA
or CLKB and
CLKB
to V
CC
- 2V. Alternatively,
if the inputs are differentially terminated with 100
, they
accept an LVDS input signal.
The LVDS input signal must adhere to the specifications
given in the
Electrical Characteristics
table. Note that the
signal must be at least 1.2V to be a valid logic HIGH.
Applications Information
Output Termination
Terminate the outputs with 100
across each differen-
tial pair (Q_ to
Q_
). Ensure that output currents do not
exceed the current limits as specified in the
Absolute
Maximum Ratings
table. Under all operating conditions,
observe the device
’
s total thermal limits.
Power-Supply Bypassing
Bypass each V
CC
pin to ground with high-frequency sur-
face-mount ceramic 0.1μF and 0.01μF capacitors in par-
allel and as close to the device as possible, with the
0.01μF capacitor closest to the device. Use multiple par-
allel vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals. Use
50
traces for CLK_,
CLK_
, Q_, and
Q_
. Maintaining
integrity is accomplished in part by reducing signal
reflections and skew, and increasing common-mode
noise immunity by keeping the differential traces close
together.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, and not using sharp corners or vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 1119
PROCESS: Bipolar
M
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
_______________________________________________________________________________________
7
MAX9317
MAX9317A
MAX9317B
MAX9317C
TQFP (7mm x 7mm)
TOP VIEW
TOP VIEW
32
28
29
30
31
25
26
27
Q
V
C
V
C
10
13
15
14
16
11
12
9
V
C
V
C
Q
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
GND
CLKA
N.C. (V
TA
)
N.C. (V
TB
)
1
GND
CLKA
CLKB
CLKB
Q
Q
Q
Q
Q
QB1
QB1
QB0
QB0
QA4
QA4
QA3
QA3
Q
Q
Q
Q
Q
MAX9317
MAX9317A
MAX9317B
MAX9317C
QFN-EP**
32
28
29
30
31
25
26
27
Q
V
C
V
C
10
13
15
14
16
11
12
9
V
C
V
C
Q
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
GND
CLKA
N.C. (V
TA
)
N.C. (V
TB
)
1
GND
CLKA
CLKB
CLKB
Q
Q
Q
Q
Q
QB1
QB1
QB0
QB0
QA4
QA4
QA3
QA3
Q
Q
Q
Q
Q
**EXPOSED PADDLE
**EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V
EE
.
( ) MAX9317A/MAX9317C.
Pin Configurations
相關(guān)PDF資料
PDF描述
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MAX9317-MAX9317C Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
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MAX931CPA+ 功能描述:校驗(yàn)器 IC Comparator w/2% Reference RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
MAX931CSA 功能描述:校驗(yàn)器 IC Comparator w/2% Reference RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
MAX931CSA+ 功能描述:校驗(yàn)器 IC Comparator w/2% Reference RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
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