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參數(shù)資料
| 型號(hào)： | MAX9315EUP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver |
| 中文描述： | LINE DRIVER, PDSO20 |
| 封裝： | 4.40 MM, TSSOP-20 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 125K |
| 代理商： | MAX9315EUP |
M
Detailed Desc ription
The MAX9315 is a low-skew, 1-to-5 differential driver
designed for clock or data distribution. A 2-to-1 MUX
selects one of the two differential clock inputs, CLK0,
CLK0
or CLK1,
CLK1
. The MUX is switched by the sin-
gle-ended SEL input. A logic low selects the CLK0,
CLK0
input and a logic high selects the
CLK1
, CLK1
input. The SEL logic threshold is set by the internal volt-
age reference V
BB
. SEL can be driven to V
CC
and V
EE
or by a single-ended LVPECL/LVECL signal. The
selected input is reproduced at five differential outputs.
S ync hronous Enable
The MAX9315 is synchronously enabled and disabled
with outputs in the low state to eliminate shortened
clock pulses.
EN
is connected to the input of an edge-
triggered D flip-flop. After power-up, drive
EN
low and
toggle the selected clock input to enable the outputs.
The outputs are enabled on the falling edge of the
selected clock input after
EN
goes low. The outputs are
set to a low state on the falling edge of the selected
clock input after
EN
goes high. The threshold for
EN
is
equal to V
BB
.
S upply
For interfacing to differential HSTL and LVPECL signals,
the V
CC
range is from +2.375V to +3.8V (with V
EE
grounded), allowing high-performance clock or data
distribution in systems with a nominal +2.5V or +3.3V
supply. For interfacing to differential LVECL, the V
EE
range is -2.375V to -3.8V (with V
CC
grounded). Output
levels are referenced to V
CC
and are considered
LVPECL or LVECL, depending on the level of the V
CC
supply. With V
CC
connected to a positive supply and
1:5 Differential LV PECL/LV ECL/HS T L
Cloc k and Data Driver
6
_______________________________________________________________________________________
Pin Desc ription
PIN
1
2
3
4
5
6
7
8
9
10
11
NAME
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
V
EE
FUNCTION
Noninverting Q0 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Inverting Q0 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Noninverting Q1 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Inverting Q1 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Noninverting Q2 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Inverting Q2 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Noninverting Q3 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Inverting Q3 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Noninverting Q4 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Inverting Q4 Output. Typically terminate with 50
resistor to V
CC
- 2V.
Negative Supply Voltage
12
SEL
Clock Select Input (Single Ended). Drive low to select the CLK0,
CLK0
input. Drive high to select the
CLK1,
CLK1
input. The SEL threshold is equal to V
BB
.
Noninverting Differential Clock Input 0. Internal 75k
pulldown to V
EE
.
Inverting Differential Clock Input 0. Internal 75k
pullup to V
CC
and 75k
pulldown to V
EE
.
13
14
CLK0
CLK0
15
V
BB
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01μF ceramic capacitor to V
CC
;
otherwise, leave open.
16
17
CLK1
CLK1
Noninverting Differential Clock Input 1. Internal 75k
pulldown to V
EE
.
Inverting Differential Clock Input 1. Internal 75k
pullup to V
CC
and 75k
pulldown to V
EE
.
18, 20
V
CC
Positive Supply Voltage. Bypass V
CC
to V
EE
with 0.1μF and 0.01μF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
19
EN
Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock
input when
EN
is low. Outputs are synchronously driven low on the falling edge of the selected
clock input when
EN
is high.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9315EUP+ | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9315EUP+T | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9315EUP-T | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9315EUP-TG068 | 制造商:Maxim Integrated Products 功能描述:1:5 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND - Rail/Tube |
| MAX9315EVKIT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Evaluation Kit for the MAX9315 MAX9316 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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