參數(shù)資料
型號(hào)： MAX9273GTL/V+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/49頁(yè)
文件大?。?/td> 0K
描述： IC SERIALIZER 22BIT GMSL 40TQFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
12
Maxim Integrated
Pin Description (continued)
PIN
NAME
FUNCTION
15, 39
IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF
and 0.001FF capacitors as close as possible to the device with the smallest value capacitor
closest to IOVDD.
18
GPO
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input. GPO = low
upon power-up and when PWDN = low.
19
GPIO1
Open-Drain, General-Purpose Input/Output with Internal 60kI Pullup to IOVDD
20
MS
Mode-Select Input with Internal Pulldown to EP. Set MS = low to select base mode.
Set MS = high to select bypass mode.
21
PWDN
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
power-down mode to reduce power consumption.
22
DRS
Data-Rate Select Input with Internal Pulldown to EP (Table 15).
23
CONF0
Configuration 0. Three-level configuration input (Table 9).
24
CONF1
Configuration 1. Three-level configuration input (Table 9).
25
OUT-
Inverting Coax/Twisted-Pair Serial Output
26
OUT+
Noninverting Coax/Twisted-Pair Serial Output
28
RX/SDA
UART Receive or I2C Serial-Data Input/Output with Internal 30kI Pullup to IOVDD. In UART
mode, RX/SDA is the Rx input of the serializer’s UART. In the I2C mode, RX/SDA is the
SDA input/output of the serializer’s I2C master/slave. RX/SDA has an open-drain driver and
requires a pullup resistor.
29
TX/SCL
UART Transmit or I2C Serial-Clock Input/Output with Internal 30kI Pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializer’s UART. In the I2C mode, TX/SCL is the SCL
input/output of the serializer’s I2C master/slave. TX/SCL has an open-drain driver and requires
a pullup resistor.
30
AUTOS
Autostart Input with Internal Pulldown to EP. AUTOS = low enables serialization upon power-
up and automatic frequency range selection of PCLKIN. AUTOS = high puts the part in sleep
mode upon power-up.
31
PCLKIN
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and provides
the PLL reference clock.
35
DVDD
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to DVDD.
—
EP
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
ground plane through an array of vias for proper thermal and electrical performance.
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