參數(shù)資料
型號： MAX9260GCB/V+T
廠商： Maxim Integrated Products
文件頁數(shù)： 4/51頁
文件大?。?/td> 0K
描述： IC DESERIALIZER GMSL 64TQFP
標(biāo)準(zhǔn)包裝： 750
系列： *
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
12 _____________________________________________________________________________________
MAX9259 Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
TQFN
36
31
TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C
mode, TX/SCL is the SCL output of the MAX9259’s I2C master.
37
32
SSEN
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming
from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on
the serial link. Set SSEN = low to use the serial link without spread spectrum.
38
33
LMN1
Line-Fault Monitor Input 1 (see Figure 3 for details)
40, 41
34, 35
OUT-,
OUT+
Differential CML Output
-/+. Differential outputs of the serial link.
43
37
LMN0
Line-Fault Monitor Input 0 (see Figure 3 for details)
44
38
LFLT
Line Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor.
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
45
39
INT
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT
output.
46
40
DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
47
41
ES
Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup
resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on
the falling edge of PCLKIN.
48
42
BWS
Bus-Width Select. Parallel input bus-width selection input requires external pulldown or
pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.
—
EP
Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND
(TQFN package). MUST externally connect EP to the AGND plane to maximize thermal
and electrical performance.
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