參數(shù)資料
型號(hào): MAX9246GUM+D
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/23頁(yè)
文件大?。?/td> 0K
描述: IC 21BIT DESERIALIZER 48-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 39
功能: 解串器
數(shù)據(jù)速率: 306Mbps
輸入類(lèi)型: LVDS
輸出類(lèi)型: LVTTL,LVCMOS
輸入數(shù): 3
輸出數(shù): 21
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________
15
spread-spectrum PLL locks immediately after (see
Figure 16). If the spread-spectrum PLL loses lock, it
locks again with only one PLL lock delay (see Figure 17).
AC-Coupling Benefits
Bit errors experienced with DC-coupling (Figure 18)
can be eliminated by increasing the receiver common-
mode voltage range through AC-coupling. AC-coupling
increases the common-mode voltage range of an LVDS
receiver to nearly the voltage rating of the capacitor. The
typical LVDS driver output is 350mV centered on a 1.25V
offset voltage, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately
±1V common-
mode difference between the driver and receiver on a
RPLLS2 (32,800 x RCIP)
±2% OR ±4% SPREAD
±4% OR ±2% SPREAD
LOW
SSG
RxCLKOUT
RxOUT_
Figure 13. Output Waveforms when Spread Amount is Changed
RPLLS2 (32,800 x RCIP)
±2% OR ±4% SPREAD
LOW
NO SPREAD
SSG
RxCLKOUT
RxOUT_
Figure 14. Output Waveforms when Spread is Added
RPLLS2 (32,800 x RCIP)
NO SPREAD
±4% OR ±2% SPREAD
SSG
RxCLKOUT
RxOUT_
DATA SWITCHING BUT NOT VALID
Figure 15. Output Waveforms when Spread is Removed
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