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    • 參數(shù)資料
      型號(hào): MAX9222
      廠商: Maxim Integrated Products, Inc.
      英文描述: Programmable DC-Balance 21-Bit Deserializers
      中文描述: 可編程、直流平衡、21位解串器
      文件頁(yè)數(shù): 4/10頁(yè)
      文件大?。?/td> 498K
      代理商: MAX9222
      E
      vide the circuit into two circuits, cut open the PC board
      trace shorting the resistor pads at R41
      R45, R49, R50,
      R75, remove resistor R39, and install a shorting resistor
      on R48.
      The MAX9205 (U1) serializer circuit generates two
      types of signals, synchronization and serialized data
      patterns:
      1) Generate synchronization (SYNC) patterns by apply-
      ing a high-state LVCMOS signal to pin 2 of the 24-
      pin header J1 or the SYNC2 PC board pad.
      2) Generate serialized data patterns by asserting a
      low-state LVCMOS signal to pin 2 of the 24-pin
      header J1 and provide 10-bit parallel data to the EV
      kit. For data and clock input signal details, see the
      Input Signal
      and
      Clock Signal
      sections, respectively.
      The serializer
      s BLVDS output signal is a 12-bit serial
      pattern that consists of a high-state start bit and low-
      state end bit, added internally and used by the deseri-
      alizer, to the 10-bit parallel input data. Refer to the
      MAX9205/MAX9207 data sheet for details. To monitor
      the BLVDS output signal, connect a differential signal
      probe to JU9 (noninverting single-ended signal) or
      JU10 (inverting single-ended signal) or connect twist-
      ed-pair cable to PC board vias 1A (noninverting signal)
      and 1B (inverting signal). Terminate the twisted pair at
      the far end with a 100
      resistor for a total 50
      load.
      See Table 4 for locations and connector type for the
      LVDS serial signal output.
      To evaluate the MAX9206 (U2) deserializer circuit, pro-
      vide a 12-bit BLVDS serial input and a clock signal to
      the REFCLK SMA connector. Bit 0 of the 12-bit serial
      input pattern should be BLVDS high state and bit 11
      should be BLVDS low state with data bit in between.
      Refer to the MAX9206/MAX9208 data sheet for further
      details on the start and end bits.
      The 12-bit BLVDS pattern can be supplied to the dese-
      rializer circuit in two ways: with twisted-pair cable or
      SMA connectors:
      1) Using twisted-pair cable, connect the serial input
      signal to PC board vias 2A (noninverting signal) and
      2B (inverting signal). Terminate the twisted-pair
      cable at the transmitting end with a 100
      resistor for
      a total 50
      load (including the 100
      resistor in par-
      allel at the deserializer input).
      2) With SMA connectors, install shorting resistors at the
      R46 and R47 PC board pads and connect the serial
      signal through SMA connectors INA (noninverting
      signal) and INB (inverting signal). Monitor the integri-
      MAX9205 Evaluation Kit
      4
      _______________________________________________________________________________________
      SIGNAL
      Input/J1
      Output/J2
      BIT 0
      J1-4
      J2-1
      BIT 1
      J1-6
      J2-3
      BIT 2
      J1-8
      J2-5
      BIT 3
      J1-10
      J2-7
      BIT 4
      J1-12
      J2-9
      BIT 5
      J1-14
      J2-11
      BIT 6
      J1-16
      J2-13
      BIT 7
      J1-18
      J2-15
      BIT 8
      J1-20
      J2-17
      BIT 9
      J1-22
      J2-19
      Table 2. Input/Output Bit Location
      HEADER
      JU16
      JU17
      JU18
      JU19
      JU20*
      JU21*
      JU22*
      JU23
      JU24
      JU25
      JU26*
      JU27*
      BIT/SIGNAL
      0
      1
      2
      3
      4
      5
      6
      7
      8
      9
      LOCK
      RCLK
      Table 3. Individual Parallel Outputs
      SIGNAL
      N O N N VER T N G
      SIG N A L
      INVERTING
      SIGNAL
      CONNECTOR
      Serializer
      (U1) Output
      PC board
      via 1A
      PC board
      via 1B
      Plated through
      holes for
      twisted- pair
      (TP) cable
      Serializer
      (U1) Output
      Header JU9
      Header
      JU10
      Differential
      signal probe
      Deserializer
      (U2) Input
      PC board
      via 2A (user
      input)
      PC board
      via 2B (user
      input)
      Plated through
      holes for TP
      cable
      Deserializer
      (U2) Input
      Header JU12
      Header
      JU13
      Differential
      signal probe
      Table 4. LVDS Signals and Connections
      *
      Headers are not in sequential order on the EV kit board.
      相關(guān)PDF資料
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      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      MAX9222ETM 制造商:Maxim Integrated Products 功能描述:- Rail/Tube
      MAX9222EUM 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers
      MAX9222EUM+ 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube
      MAX9222EUM+D 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube
      MAX9222EUM+T 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Tape and Reel