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參數(shù)資料
| 型號： | MAX9220EUM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER PROG 48TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 3 |
| 輸出數(shù)： | 21 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________
7
Detailed Description
The MAX9210/MAX9220 operate at a parallel clock fre-
quency of 8MHz to 34MHz in DC-balanced mode and
10MHz to 40MHz in non-DC-balanced mode. The
MAX9214/MAX9222 operate at a parallel clock frequency
of 16MHz to 66MHz in DC-balanced mode and 20MHz to
85MHz in non-DC-balanced mode. The transition times of
the single-ended outputs are increased on the
MAX9210/MAX9220 for reduced EMI.
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB/NC pin (see Table 1 for DCB/NC
default settings and operating modes). In non-DC-bal-
anced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2 DC-
balance bits). The highest data rate in DC-balanced
mode for the MAX9214 and MAX9222 is 66MHz x 9 =
594Mbps. In non-DC-balanced mode, the maximum
data rate is 85MHz x 7 = 595Mbps.
DC Balance
Data coding by the MAX9209/MAX9213 serializers
(which are companion devices to the MAX9210/
MAX9214/MAX9220/MAX9222 deserializers) limits the
imbalance of ones and zeros transmitted on each chan-
nel. If +1 is assigned to each binary 1 transmitted and -1
is assigned to each binary 0 transmitted, the variation in
the running sum of assigned values is called the digital
sum variation (DSV). The maximum DSV for the data
channels is 10. At most, 10 more zeros than ones, or 10
more ones than zeros, are transmitted. The maximum
DSV for the clock channel is five. Limiting the DSV and
choosing the correct coupling capacitors maintains dif-
ferential signal amplitude and reduces jitter due to
droop on AC-coupled links.
VCC - 0.3V
VCC
RIN2
RIN1
RxIN_ + OR
RxCLK IN+
RxIN_ - OR
RxCLK IN-
RIN1
RxIN_ + OR
RxCLK IN+
RxIN_ - OR
RxCLK IN-
RIN1
NON-DC-BALANCED MODE
DC-BALANCED MODE
1.2V
Figure 1. LVDS Input Circuits
Table 1. DC-Balance Programming
DEVICE
DCB/NC
OUTPUT STROBE
EDGE
OPERATING MODE
OPERATING
FREQUENCY (MHz)
High or open
DC balanced
8 to 34
MAX9210
Low
Rising
Non-DC balanced
10 to 40
High or open
DC balanced
16 to 66
MAX9214
Low
Rising
Non-DC balanced
20 to 85
High or open
DC balanced
8 to 34
MAX9220
Low
Falling
Non-DC balanced
10 to 40
High or open
DC balanced
16 to 66
MAX9222
Low
Falling
Non-DC balanced
20 to 85
RCIP
RxCLK OUT
ODD RxOUT
EVEN RxOUT
RISING EDGE STROBE SHOWN.
Figure 2. Worst-Case Test Pattern
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9222 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9222ETM | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX9222EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9222EUM+ | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+D | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
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