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參數(shù)資料
| 型號(hào)： | MAX9205EAI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Positive-Edge-Triggered Flip-Flops W/Clear And Preset 20-LCCC -55 to 125 |
| 中文描述： | LINE DRIVER, PDSO28 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 180K |
| 代理商： | MAX9205EAI |
Applications Information
Power-Supply Bypassing
Bypass AV
CC
with high-frequency surface-mount
ceramic 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AV
CC
. Bypass DV
CC
with high-fre-
quency surface-mount ceramic 0.1μF and 0.001μF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DV
CC
.
Differential Traces and Termination
Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100
termination, the
output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90
°
turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
M
10-Bit Bus LVDS Serializers
_______________________________________________________________________________________
7
OUT+
OUT-
V
OD
V
OS
R
L
2
R
L
2
Figure 1. Output Voltage Definitions
TCLK
ODD IN_
EVEN IN_
TCLK_R/F = LOW
Figure 2. Worst-Case I
CC
Test Pattern
TCLK
t
CLKT
10%
90%
90%
10%
t
CLKT
0
3V
Figure 3. Input Clock Transition Time Requirement
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9205EAI/V+ | 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9205EAI/V+T | 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9205EAI+ | 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9205EAI+/V+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX9205EAI+/V+T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
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