參數(shù)資料
型號: MAX9179EUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Quad LVDS Receiver with Hysteresis
中文描述: QUAD LINE RECEIVER, PDSO16
封裝: 4.40 MM, TSSOP-16
文件頁數(shù): 7/11頁
文件大?。?/td> 289K
代理商: MAX9179EUE
M
Quad LVDS Receiver with Hysteresis
__________________________________________________________________________
Pin Description
PIN
TSSOP
1
2
3
4
5
6
7
8
QFN
15
16
1
2
3
4
5
6
NAME
FUNCTION
IN1-
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
Inverting LVDS Input 1
Noninverting LVDS Input 1
Noninverting LVDS Input 2
Inverting LVDS Input 2
Inverting LVDS Input 3
Noninverting LVDS Input 3
Noninverting LVDS Input 4
Inverting LVDS Input 4
9
7
EN
Enable Complementary Input. The outputs are active when EN = high and
EN
= low or open. For
all other combinations of EN and
EN
, the outputs are disabled and in high impedance.
10
11
12
13
14
15
8
9
10
11
12
13
OUT4
OUT3
GND
V
CC
OUT2
OUT1
LVCMOS/LVTTL Output 4
LVCMOS/LVTTL Output 3
Ground
Power-Supply Input. Bypass V
CC
to GND with 0.1μF and 0.001μF ceramic capacitors.
LVCMOS/LVTTL Output 2
LVCMOS/LVTTL Output 1
16
14
EN
Enable Input. The outputs are active when EN = high and
EN
= low or open. For all other
combinations of EN and
EN
, the outputs are disabled and in high impedance.
EP
Exposed
Pad
Exposed Pad. Connect to ground.
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