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參數(shù)資料
| 型號： | MAX9173EUE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe |
| 中文描述： | QUAD LINE RECEIVER, PDSO16 |
| 封裝： | 4.40 MM, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 285K |
| 代理商： | MAX9173EUE |
M
Detailed Description
LVDS is a signaling method intended for point-to-point
communication over a controlled-impedance medium
as defined by the ANSI TIA/EIA-644 and IEEE 1596.3
standards. LVDS uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI and system susceptibility to noise.
The MAX9173 is a 500Mbps, four-channel LVDS receiv-
er intended for high-speed, point-to-point, low-power
applications. Each channel accepts an LVDS input and
translates it to an LVTTL/LVCMOS output. The receiver
is specified to detect differential signals as low as
100mV and as high as 1.2V within an input voltage
range of 0 to V
CC
. The 250mV to 400mV differential out-
put of an LVDS driver is nominally centered around a
1.2V offset. This offset, coupled with the receiver
’
s 0 to
V
CC
input voltage range, allows more than ±1V shift in
the signal (as seen by the receiver). This allows for a
difference in ground references of the transmitter and
the receiver, the common-mode effects of coupled
noise, or both.
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
6
_______________________________________________________________________________________
PIN
TSSOP/SO
1
2
3
4
5
6
7
8
QFN
15
16
1
2
3
4
5
6
NAME
FUNCTION
IN1-
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
Inverting Differential Receiver Input for Receiver 1
Noninverting Differential Receiver Input for Receiver 1
Noninverting Differential Receiver Input for Receiver 2
Inverting Differential Receiver Input for Receiver 2
Inverting Differential Receiver Input for Receiver 3
Noninverting Differential Receiver Input for Receiver 3
Noninverting Differential Receiver Input for Receiver 4
Inverting Differential Receiver Input for Receiver 4
9, 16
7, 14
EN
, EN
Receiver Enable Inputs. When EN = high and
EN
= low or open, the outputs are active.
For other combinations of EN and
EN
, the outputs are disabled and in high
impedance.
10
11
12
8
9
10
OUT4
OUT3
GND
LVCMOS/LVTTL Receiver Output for Receiver 4
LVCMOS/LVTTL Receiver Output for Receiver 3
Ground
13
11
V
CC
Power-Supply Input. Bypass V
CC
to GND with 0.1μF and 0.001μF ceramic capacitors.
Place the smaller value cap as close to the pin as possible.
14
15
—
12
13
OUT2
OUT1
EP
LVCMOS/LVTTL Receiver Output for Receiver 2
LVCMOS/LVTTL Receiver Output for Receiver 1
Exposed Pad. Solder to ground plane for proper heat dissipation.
Exposed Pad
Pin Description
ENABLES
INPUTS
(IN_+) - (IN_-)
V
ID
≥
0
V
ID
≤
-100mV
OUTPUT
OUT_
H
L
H
Z
EN
EN
H
L or open
Open, undriven short, or undriven parallel termination
Don
’
t care
All other combinations of ENABLE pins
Table 1. Input/Output Function Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9174ETB | 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
| MAX9174EUB | 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
| MAX9175ETB | 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
| MAX9175EUB | 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
| MAX9178ETE | Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9173EUE+ | 制造商:Maxim Integrated Products 功能描述:LINE RCVR 4RX 16TSSOP - Rail/Tube |
| MAX9173EUE+T | 制造商:Maxim Integrated Products 功能描述:LINE RCVR 4RX 16TSSOP - Tape and Reel |
| MAX9173EUE-T | 制造商:Maxim Integrated Products 功能描述:QUAD LVDS LINE RECEIVER WITH FLOW-THROUGH PIN - Tape and Reel |
| MAX9174 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
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