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參數(shù)資料
| 型號(hào)： | MAX9159ESA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual LVDS Line Receiver |
| 中文描述： | DUAL LINE RECEIVER, PDSO8 |
| 封裝： | 0.150 INCH, MS-012A, SOIC-8 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 147K |
| 代理商： | MAX9159ESA |
M
Dual LVDS Line Receiver
_______________________________________________________________________________________
5
0.6
0.5
0.4
0.3
0.2
-40
10
-15
35
60
85
TRANSITION TIME vs. TEMPERATURE
M
TEMPERATURE (
°
C)
T
t
F
t
R
2.0
2.4
2.2
2.8
2.6
3.0
3.2
3.4
3.6
10
20
LOAD CAPACITANCE (pF)
25
15
30
35
40
45
50
PROPAGATION DELAY
vs. LOAD CAPACITANCE
M
P
t
PHL
t
PLH
0
0.4
0.2
0.6
1.0
0.8
1.4
1.2
1.6
2.0
1.8
2.2
10
20
LOAD CAPACITANCE (pF)
25
15
30
35
40
45
50
TRANSITION TIME
vs. LOAD CAPACITANCE
M
T
t
F
t
R
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, |V
ID
| = 200mV, V
CM
= 1.2V, f
IN
= 200MHz, C
L
= 10pF, T
A
= +25
°
C, unless otherwise noted.)
Detailed Description
LVDS is intended for point-to-point communication over
a controlled-impedance medium as defined by the
ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS
uses a lower voltage swing than other common commu-
nication standards, achieving higher data rates with
reduced power consumption, while reducing EMI
emissions and system susceptibility to noise.
The MAX9159 is a dual LVDS line receiver ideal for
applications requiring high data rates, low power, and
low noise. The device accepts an LVDS input and
translates it to an LVTTL output. The receiver detects
differential signals as low as 100mV and as high as
0.6V within an input voltage range of 0 to 2.4V.
The 250mV to 450mV differential output of an LVDS dri-
ver is nominally centered around a 1.25V offset. This
offset, coupled with the receiver
’
s 0 to 2.4V input volt-
age range, allows an approximate ±1V shift in the sig-
nal (as seen by the receiver). This allows for a
difference in ground references of the driver and the
receiver, the common-mode effects of coupled noise,
or both. The LVDS standards specify an input voltage
range of 0 to 2.4V referenced to receiver ground.
Fail-Safe
The fail-safe feature of the MAX9159 sets the output
high and reduces supply current when:
Inputs are open.
Inputs are undriven and shorted.
Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the input may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when an LVDS driver output is in high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to V
CC
- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage is
less than V
CC
- 0.3V and the fail-safe circuit is not acti-
PIN
1
2
3
4
5
6
7
8
NAME
V
CC
1Y
2Y
GND
2B
2A
1B
1A
FUNCTION
Power Supply
Channel 1 Output
Channel 2 Output
Ground
Channel 2 Inverting Differential Input
Channel 2 Noninverting Differential Input
Channel 1 Inverting Differential Input
Channel 1 Noninverting Differential Input
Pin Description
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