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lel as close to the device as possible, with the smaller
value capacitor closest to VCC.
Differential Traces
Trace characteristics affect the performance of the
MAX9152. Use controlled-impedance traces. Eliminate
reflections and ensure that noise couples as common
mode by running the differential trace pairs close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90
° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have nominal differential
impedance of 75
or 100. Use cables and connec-
tors that have matched differential impedance to mini-
mize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the differential receiver.
Board Layout
For LVDS applications, a four-layer printed-circuit (PC)
board that provides separate power, ground, and sig-
nal planes is recommended.
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________
9
20%
50%
tPLHD AND tPHLD ARE MEASURED FOR ANY COMBINATION OF SEL0 AND SEL1.
80%
VID = (VIN_+) - (VIN_-)
VOD = (VOUT_+) - (VOUT_-)
VOD = 0
VID = 0
VOD = 0
+VOD
-VOD
tLHT
tHLT
VOUT_-
VOUT_+
VIN_-
VIN_+
tPLHD
tPHLD
Figure 6. Output Transition Time and Propagation Delay Timing
Diagram
tCCS IS MEASURED WITH SEL0 = SEL1 = HIGH OR LOW
(1:2 SPLITTER MODE)
VOD = (VOUT_+) - (VOUT_-)
VOD = 0
VOUT1-
VOUT1+
VOUT0-
VOUT0+
tCCS
Figure 7. Output Channel-to-Channel Skew
OUT0
OUT0 OR OUT1
OUT1
2 x 2 CROSSPOINT
2:1 MUX
1:2 DEMUX
1:2 SPLITTER
DUAL REPEATER
OUT0
OUT1
OUT0
OUT1
OUT0
OUT1
IN0
IN1
IN0
IN1
IN0
IN1
IN0 OR IN1
Figure 8. Programmable Configurations