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Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled impedance medium, as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9150 is a 400Mbps, 10-port LVDS repeater
intended for high-speed, point-to-point, low-power
applications. This device accepts an LVDS input and
repeats it on 10 LVDS outputs. The device is capable of
detecting differential signals as low as 100mV and as
high as 1V within a 0 to 2.4V input voltage range. The
LVDS standard specifies an input voltage range of 0 to
2.4V referenced to ground.
The MAX9150 outputs use a current-steering configura-
tion to generate a 5mA to 9mA output current. This cur-
rent-steering approach induces less ground bounce
and no shoot-through current, enhancing noise margin
and system speed performance. The driver outputs are
short-circuit current limited, and are high impedance
(to ground) when
PWRDN
= low or the device is not
powered. The outputs have a typical differential resis-
tance of 240
.
The MAX9150 current-steering architecture requires a
resistive load to terminate the signal and complete the
transmission loop. Because the device switches the
direction of current flow and not voltage levels, the out-
put voltage swing is determined by the total value of
the termination resistors multiplied by the output cur-
rent. With a typical 6.4mA output current, the MAX9150
produces a 320mV output voltage when driving a trans-
mission line terminated at each end with a 100
termi-
nation resistor (6.4mA x 50
= 320mV). Logic states
are determined by the direction of current flow through
the termination resistors.
Fail-Safe
Fail-safe is a receiver feature that puts the output in a
known logic state (high) under certain fault conditions.
The MAX9150 outputs are differential high when the
inputs are undriven and open, terminated, or shorted
(Table 1).
M
Low-Jitter, 10-Port LVDS Repeater
6
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Table 1. Input/Output Function Table
INPUT, V
ID
OUTPUTS, V
OD
High
Low
High
High
High
+100mV
-100mV
Open
Short
Terminated
Undriven
Note:
V
ID
= RIN+ - RIN-, V
OD
= DO_+ - DO_-
High = 450mV > V
OD
> 250mV
Low = -250mV > V
OD
> -450mV
PIN
NAME
FUNCTION
1, 3, 11, 13,
16, 18, 20,
24, 26, 28
2, 4, 12, 14,
15, 17, 19,
23, 25, 27
DO2+, DO1+, DO10+,
DO9+, DO8+, DO7+,
DO6+, DO5+, DO4+, DO3+
DO2-, DO1-, DO10-, DO9-,
DO8-, DO7-,
DO6-, DO5-, DO4-, DO3-
Differential LVDS Outputs. Connect a 100
resistor across each of the output
pairs (DO_+ and DO_-) adjacent to the IC, and connect a 100
resistor at the
input of the receiving circuit.
5
PWRDN
Power Down. Drive
PWRDN
low to disable all outputs and reduce supply current
to 60μA. Drive
PWRDN
high for normal operation.
6, 9, 21
GND
Ground
10, 22
V
CC
Power. Bypass each V
CC
pin to GND with 0.1μF and 1nF ceramic capacitors.
7
RIN+
8
RIN-
LVDS Receiver Inputs. RIN+ and RIN- are high-impedance inputs. Connect a
resistor from RIN+ to RIN- to terminate the input signal.
Pin Description