
MAX9132/MAX9134/MAX9135
Programmable, High-Speed, Multiple
Input/Output LVDS Crossbar Switches
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13
face. The routing action takes place after correct check-
sum verification. The LIN status register (0x00) holds the
error flags for the LIN transceiver. For a write, the master
writes 2 bytes of data to the registers (0x01, 0x02). For a
read, the slave outputs the contents of registers 0x00,
0x01, and 0x02, along with the stuffing byte at a constant
value (0xFF). In either mode, the checksum follows at the
end of the data bytes. Figure 3 shows the write and read
signal frame format. Figure 4 shows the LIN write and
read data frame.
LIN-Protected Identifier
The LIN bus uses the 8-bit protected identifier (PID) to
address the slave nodes. Two parity bits (MSBs) along
with 6 ID bits (LSBs) make up the PID field. Table 4
defines the sets of the identifiers for the write/read
operations of the LIN slave node. AS0 selects the iden-
tifiers. AS1/NSLP becomes the NSLP output for activat-
ing the LIN driver chip (MAX13020).
LIN Error Handling
Register 0x00 contains the error flags found in the LIN
signal by the slave note (Table 5). A successful LIN
read resets register 0x00.
Pin Control by S[5:0] (MAX9134/MAX9135)
For the MAX9134/MAX9135, the routing can be con-
trolled by the hardware pins (S[5:0]). If the I2C register
0xFF is not written by 0xFF, then chip routing is deter-
mined by S[5:0]. Also, these pins set the initial power-
up routing condition of the chip. Table 6a gives the
details of the routing control for the MAX9134. Table 6b
gives the details of the routing control for the MAX9135.
Once the I2C register 0xFF is written by 0xFF, the I2C
registers 0x01 and 0x02 take over the routing and the
pin (S[5:0]) setting is ignored. After the I2C routing
takes place, the pin setting can be changed without
affecting the routing. The new pin setting takes effect if
the PD pin or the chip supply is toggled. Usually, once
I2C controls the routing, there is no value in using the
pin routing.
Applications Information
3-Level Inputs
The MAX9132/MAX9134/MAX9135 use several 3-level
inputs to control the device. Use three-state logic to
realize the 3-level logic using digital control.
Alternatively, if a high-impedance output is unavailable,
apply a voltage of VDD/2 to realize the midlevel high-
impedance state.
WRITE ID
READ ID
AS0
ID[5:0]
PID FIELD
ID[5:0]
PID FIELD
Low
0x08
0x27
0xE7
Open
0x0A
0xCA
0x29
0xE9
High
0x1C
0x9C
0x2B
Table 4. LIN Identifiers for Write and Read Operations
REGISTER BIT(S)
DESCRIPTION
FUNCTION
D[7:5]
Reserved
D4
Sync
Sync pulse widths outside the given tolerances detected
D3
Transmit
Value read on RXD different from value transmitted on TXD during a read
D2
Checksum
Checksum sent during a write does not match the expected checksum
D1
Parity
ID parity bit does not match expected parity
D0
Frame
Message frame did not complete within the maximum allowed time
Table 5. Register 0x00 Error Flag Mapping for LIN
MAX9132
MAX9134
MAX9135
VBAT
MAX13020
VDD
INH
TXD
RXD
NSLP
LIN
BUS
TXD
5kΩ
RXD
NSLP
NWAKE
LIN
Figure 5. Connecting the MAX9132/MAX9134/MAX9135 to the
MAX13020