參數(shù)資料
型號(hào): MAX9121EUE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 12/12頁(yè)
文件大?。?/td> 0K
描述: IC RCVR QUAD LVDS 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 接收器
驅(qū)動(dòng)器/接收器數(shù): 0/4
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
Board Layout
Because the MAX9121/MAX9122 feature a flow-through
pinout, no special layout precautions are required.
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input LVDS signals
from each other to prevent coupling. Isolate the output
LVCMOS/LVTTL signals from each other to prevent
coupling. Separate the input LVDS signals from the out-
put signals planes with the power and ground planes
for best results.
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
_______________________________________________________________________________________
9
IN_+
EN
IN_-
OUT_
DEVICE
UNDER
TEST
1/4 MAX9121/MAX9122
CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS.
S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
GENERATOR
50
CL
RL
S1
VCC
Figure 4. High-Impedance Delay Test Circuit
Figure 5. High-Impedance Delay Waveforms
1.5V
EN WHEN EN = GND OR OPEN
EN WHEN EN = VCC
OUTPUT WHEN
VID = -100mV
OUTPUT WHEN
VID = +100mV
1.5V
0.5V
tPLZ
tPHZ
tPZL
tPZH
1.5V
3V
0
3V
VCC
VOL
VOH
GND
0
50%
Chip Information
TRANSISTOR COUNT: 1354
PROCESS: CMOS
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