參數(shù)資料
型號: MAX9111
廠商: Maxim Integrated Products, Inc.
英文描述: Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23
中文描述: 單/雙路LVDS線接收器,提供超低脈沖偏差,SOT23封裝
文件頁數(shù): 8/12頁
文件大小: 183K
代理商: MAX9111
__________ Applications Information
Supply Bypassing
Bypass V
CC
with high-frequency surface-mount ceram-
ic 0.1μF and 0.001μF capacitors in parallel, as close to
the device as possible, with the 0.001μF valued capaci-
tor the closest to the device. For additional supply
bypassing, place a 10μF tantalum or ceramic capacitor
at the point where power enters the circuit board.
Differential Traces
Output trace characteristics affect the performance of
the MAX9111/MAX9113. Use controlled impedance
traces to match trace impedance to both transmission
medium impedance and the termination resistor.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90
°
turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a differential charac-
teristic impedance of about 100
. Use cables and con-
nectors that have matched impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination
Termination resistors should match the differential char-
acteristic impedance of the transmission line. Because
the MAX9111/MAX9113 are current steering devices,
an output voltage will not be generated without a termi-
nation resistor. Output voltage levels depend upon the
value of the termination resistor. Resistance values may
range from 75
to 150
.
Minimize the distance between the termination resistor
and receiver inputs. Use a single 1% to 2% surface-
mount resistor across the receiver inputs.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input and LVDS
signals from each other to prevent coupling. For best
results, separate the input and LVDS signal planes with
the power and ground planes.
M
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
8
_______________________________________________________________________________________
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
R
C
1M
R
D
1500
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 3a. Human Body ESD Test Modules
Figure 3b. Human Body Current Waveform
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