參數(shù)資料
型號(hào): MAX8884YEREKE+T
廠商: Maxim Integrated
文件頁數(shù): 13/17頁
文件大?。?/td> 579K
描述: IC REG TRPL BCK/LINEAR 16UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 2MHz
電壓/電流 - 輸出 1: 1.2 V/1.8 V,700mA
電壓/電流 - 輸出 2: 1.2 V/1.8 V,300mA
電壓/電流 - 輸出 3: 1.2 V/1.8 V,300mA
帶 LED 驅(qū)動(dòng)器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 16-UCSP(4x4)
包裝: 帶卷 (TR)
700mA DC-DC Step-Down Converters
with Dual 300mA LDO in 2mm x 2mm CSP
______________________________________________________________________________________ 13
Reference Noise
Bypass Capacitor Selection
The REFBP capacitor reduces the output noise of LDO1
and LDO2. A value of 0.033礔 is sufficient for most appli-
cations. This value can be increased up to 0.150礔 with
some effect on the soft-start time of the LDOs. See the
Typical Operating Characteristicsfor more information.
Do not use values greater than 0.150礔 as this degrades
the performance of the internal reference voltage and has
a corresponding impact on all output voltages.
Ceramic capacitors with X5R or X7R dielectric are high-
ly recommended due to their small size, low ESR, and
small temperature coefficients. Note that some ceramic
dielectrics exhibit large capacitance and ESR variation
with temperature. With dielectrics such as Z5U and
Y5V, it may be necessary to use two times the recom-
mended value to achieve desired output noise perfor-
mance at temperatures below -10癈. Tantalum
capacitors are not recommended.
Thermal Considerations
In most applications, the MAX8884Y/MAX8884Z do not
dissipate much heat due to their high efficiency. But in
applications where the MAX8884Y/MAX8884Z run at high
ambient temperature with heavy loads, the heat dissipat-
ed may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
+160癈, all power switches are turned off and LX and FB
become high impedance, and LDO1 and LDO2 are
pulled down to ground through an internal 100&resistor.
The MAX8884Y/MAX8884Z maximum power dissipation
depends on the thermal resistance of the IC package
and circuit board, the temperature difference between
the die junction and ambient air, and the rate of airflow.
The power dissipated in the device, P
DISS
, is:
where ?/DIV>
BUCK
is the efficiency of the DC-DC step-down
converter, and P
BUCK
is the output power of the DC-DC
step-down converter.
The maximum allowed power dissipation, P
MAX
, is:
where (T
JMAX
- T
A
) is the temperature difference
between the MAX8884Y/MAX8884Z die junction and
the surrounding air, and ?/DIV>
JA
is the thermal resistance of
the junction through the PCB, copper traces, and other
materials to the surrounding air.
PCB Layout
High switching frequencies and relatively large peak
currents make the PCB layout a very important part of
design. Good design minimizes excessive EMI on the
feedback paths and voltage gradients in the ground
plane, resulting in a stable and well regulated output.
Minimize the ground loop formed by C
IN1
, C
BUCK
, and
PGND. To do this, connect C
IN1
close to IN1A/IN1B
and PGND. Connect the inductor and output capacitor
as close as possible to the IC and keep their traces
short, direct, and wide. Keep noisy traces, such as the
LX node, as short as possible. Connect AGND and
PGND to the common ground plane. Figure 1 illustrates
an example PCB layout and routing scheme.
P
T
T
MAX
J MAX  A
JA
=

(
)
_
?/DIV>
P    P
BUCK
I    V   V
I    V   V
DISS  BUCK
LDO  IN   LDO  LDO  IN   LDO
=

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+

+

1
1
1  2
1
2   2
2
?/DIV>
(
)
(
)
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