參數(shù)資料
型號(hào): MAX814
廠商: Maxim Integrated Products, Inc.
英文描述: Accuracy, Low-Power, +3V and +5V μp Supervisory Circuits(高精度,±1%,低功耗,3V和5VμP監(jiān)控電路)
中文描述: ±1%精度、低功耗、+3V與+5V微處理器監(jiān)控電路
文件頁數(shù): 12/16頁
文件大?。?/td> 154K
代理商: MAX814
M
where C
HOLD
is the capacitance (in Farads), I
LOAD
is
the current being drained from the capacitor (in
Amperes), and V
LR
is the low-line to reset threshold dif-
ference (in Volts).
Manual Reset
Many μP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MR is low,
and for t
RS
(200ms) after MR returns high. This input
has an internal pull-up resistor, so it can be left open if
not used. MR can be driven with TTL/CMOS-logic lev-
els or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual-reset function; external
debounce circuitry is not required.
The watchdog circuit can be used to force a reset in
the MAX815 by connecting WDO to MR. If MR is driven
from long cables, or the device is used in a noisy envi-
ronment, connect a 0.1μF capacitor to ground to pro-
vide additional noise immunity.
__________Applic ations Information
Low-V oltage Operation
The LOW LINE, PFO, and WDO outputs will be locked to
logic low when the power supply drops below the lock-
out threshold (typically 1V below the reset threshold).
Ensuring a V alid
RES ET Output Down to V
CC
= 0V
When V
CC
falls below 1V, the RESET output no longer
sinks current, but becomes an open circuit. High-
impedance CMOS-logic inputs can drift to undeter-
mined voltages if left undriven. If a pull-down resistor is
added to the RESET pin as shown in Figure 10, any
stray charge or leakage currents will be drained to
ground, holding RESET low. Resistor value R1 is not
critical. It should be about 100k
—large enough not to
load RESET, and small enough to pull RESET to
ground.
±1% Ac c urac y, Low-Power, +3V and +5V
μP S upervisory Circ uits
12
______________________________________________________________________________________
Figure 9. Timing Diagram
V
LL
V
CC
0
0
0
V
CC
V
CC
V
CC
V
LLT
60mV
V
RT
V
RT
t
RS
t
MR
t
MD
t
RS
LOW LINE
(MAX814)
WDO
(MAX815)
MR
RESET
Figure 8. MAX815 Watchdog Timing
V
CC
0V
V
CC
0V
V
CC
0V
V
CC
0V
MR
WDI
WDO
RESET
RESET
t
WD
t
WP
t
WD
t
WD
t
WDO
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