參數(shù)資料
型號(hào): MAX7432
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125
中文描述: 標(biāo)準(zhǔn)清晰度、視頻重建濾波器及緩沖器
文件頁數(shù): 12/21頁
文件大?。?/td> 444K
代理商: MAX7432
M
Standard Definition Video Reconstruction
Filters and Buffers
12
______________________________________________________________________________________
Programming the
MAX7428/MAX7430/MAX7432
An address sequence precedes a write or read opera-
tion to determine with which device to communicate. If
the address transmitted in this mode matches with a
device
s address, the device and μP can initiate data
transfer. When entering the four address bits, ensure
that the LSB is entered first. The following is the com-
mand sequence and timing diagram (Figure 6) for an
address sequence.
Use a write sequence to load data into the data register
of the device. It must follow an address sequence.
Transmit a minimum of eight data bits for the MAX7428,
16 data bits for the MAX7430, or 24 data bits for the
MAX7432 to make this transaction valid starting with
the LSB first. The last 8/16/24 data bits are used if more
than 8/16/24 bits are loaded into the register. The fol-
lowing is the command sequence and timing diagram
(Figure 7) for a write sequence.
During the read sequence, the μP sends a prompt
pulse causing the device to output the data word LSB
first. Similar to the write transaction, the read transac-
tion must be preceded by an address sequence. If
more than 8 prompts (MAX7428), 16 prompts
(MAX7430), or 24 prompts (MAX7432) are available,
the device outputs the same data starting with the LSB
again. The following is the command sequence and
timing diagram (Figure 8) for a read sequence.
Write Command Sequence:
T001
Data
8-bits (MAX7428,
See Table 1)
Data
16-bits (MAX7430,
See Table 3)
Data
24-bits (MAX7432,
See Table 5)
T111
Address Command Sequence:
T010
Address = 4-bits
T111
Initialization Command Sequence:
Initialize wait
T011
Initialize Time Address ID = 4-bits
T111
INITIALIZING TIME PERIOD (ms)
WITH R
REXT
= 300k
(t
INT
)
TYP
162 (136.8)
112
52.6 (44.1)
35.90
23.90 (13.7)
25.20 (14.4)
16.25
11.21 (4.4)
11.80 (4.64)
5.26
3.59
2.39
1.625 (1.37)
1.710 (1.44)
1.121
0.526 (0.441)
0.554 (0.464)
0.359
0.239
0.162 (0.137)
0.171 (0.144)
CAPACITOR VALUE (nF)
INITIALIZING WAIT PERIOD
(ms) (t
INTWAIT
)
MIN
MAX
1000
680
470
220
150
100
68
47
22
15
10
6.8
4.7
2.2
1.5
1
20.000
13.600
9.400
4.400
3.000
2.000
1.360
0.940
0.440
0.300
0.200
0.136
0.094
0.044
0.030
0.020
171 (144)
118
55.4 (46.4)
37.80
179 (151.2)
123
58.2 (48.72)
39.70
26.50 (15.1)
17.95
12.39 (4.9)
5.82
3.97
2.65
1.795 (1.51)
1.239
0.582 (0.487)
0.397
0.265
0.179 (0.151)
17.10
5.54
3.78
2.52
1.180
0.378
0.252
Table 7. Initialization Capacitor Values and Pulse Widths
(C
REXT
= ±10% Tolerance, R
REXT
= ±1% Tolerance)
Note:
( ) Indicates the time periods associated with 20% capacitors. This limits the maximum number of devices on the bus to seven.
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