參數(shù)資料
型號(hào): MAX6828V+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6
封裝: LEAD FREE, SOT-23, 6 PIN
文件頁數(shù): 11/12頁
文件大?。?/td> 591K
代理商: MAX6828V+T
Detailed Description
RESET/RESET Output
A microprocessor’s (P’s) reset input starts the P in a
known state. The MAX6826–MAX6831 P supervisory
circuits assert a reset to prevent code-execution errors
during power-up, power-down, and brownout condi-
tions. Whenever a monitored voltage falls below the
reset threshold, the reset output asserts low for RESET
and high for RESET. Once all monitored voltages
exceed their reset thresholds, an internal timer keeps
the reset output asserted for the specified reset timeout
period (tRP); after this interval, reset output returns to its
original state (Figure 3).
Manual Reset Input
Many P-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts a reset. Reset remains asserted while MR is
low, and for the timeout period (140ms min) after it
returns high. MR has an internal 50k
pullup resistor,
so it can be left open if not used. This input can be dri-
ven with CMOS logic levels or with open-drain/collector
MAX6826
–MAX6831
Dual Ultra-Low-Voltage SOT23 P Supervisors
with Manual Reset and Watchdog Timer
8
_______________________________________________________________________________________
MAX6829/MAX6830/MAX6831
VCC
VCC2
VCC
WDI
OR
RESET
MR
RESET TIMEOUT
DELAY GENERATOR
1.26V
0.63V
WATCHDOG
TIMER
WATCHDOG
TRANSITION
DETECTOR
Figure 2. Functional Diagram of VCC2
VCC
1V
tRD
VTH
tRD
RESET
GND
RESET
tRP
Figure 3. Reset Timing Diagram
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