參數(shù)資料
型號(hào): MAX6747KA16
廠商: Maxim Integrated Products, Inc.
英文描述: UP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
中文描述: 復(fù)位電路的電容可調(diào)的復(fù)位/看門狗超時(shí)周期
文件頁數(shù): 3/14頁
文件大小: 187K
代理商: MAX6747KA16
M
μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +1.2V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= +5V and T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
C
SWT
= 1500pF
11.38
15.18
18.98
Fast Watchdog Timeout Period,
SET Ratio = 64,
(MAX6752/MAX6753)
t
WD1
C
SWT
= 100pF
1.01
ms
Fast Watchdog Minimum Period
(MAX6752/MAX6753)
2000
ns
SWT
Ramp Current
SWT
Ramp Threshold
I
RAMP
V
RAMP
V
SWT
= 0 to 1.23V, V
CC
= 1.6V to 5V
V
CC
= 1.6V to 5V (V
RAMP
rising)
V
CC
1.0V, I
SINK
= 50μA
V
CC
2.7V, I
SINK
= 1.2mA
V
CC
4.5V, I
SINK
= 3.2mA
V
CC
1.8V, I
SOURCE
= 200μA
V
CC
2.25V, I
SOURCE
= 500μA
V
CC
4.5V, I
SOURCE
= 800μA
V
CC
> V
TH
, reset not asserted,
V
RESET
= 5.5V
200
1.173
250
1.235
300
1.297
0.3
0.3
0.4
nA
V
RESET
Output Voltage LOW
Open-Drain, Push-Pull
(Asserted)
V
OL
V
0.8 x V
CC
0.8 x V
CC
0.8 x V
CC
RESET
Output Voltage HIGH,
Push-Pull (Not Asserted)
V
OH
V
RESET
Output Leakage Current,
Open Drain
I
LKG
1.0
μA
DIGITAL INPUTS (
MR
, SET0, SET1, WDI, WDS)
V
IL
V
IH
V
IL
V
IH
0.8
V
CC
4.0V
2.4
V
CC
< 4.0V
0.3 x V
CC
Input Logic Levels
0.7 x V
CC
1
V
MR
Minimum Pulse Width
MR
Glitch Rejection
MR
to
RESET
Delay
MR
Pullup Resistance
WDI Minimum Pulse Width
RESET IN
RESET IN Threshold
RESET IN Leakage Current
RESET IN to
RESET
Delay
μs
ns
ns
k
ns
100
200
20
Pullup to V
CC
12
300
28
V
RESET IN
I
RESET IN
TA = -40
°
C to +125
°
C
1.216
-50
1.235
±
1
20
1.254
+50
V
nA
μs
RESET IN falling at 1mV/μs
Note 1:
Production testing done at T
A
= +25
°
C. Over temperature limits are guaranteed by design.
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