參數(shù)資料
型號(hào)： MAX6602UE9A+T
廠商： Maxim Integrated
文件頁(yè)數(shù)： 9/18頁(yè)
文件大?。?/td> 202K
描述： IC TEMP MONITOR 5CH 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
功能： 溫度監(jiān)控系統(tǒng)（傳感器）
傳感器類型： 內(nèi)部和外部
感應(yīng)溫度： -40°C ~ 125°C，外部傳感器
精確度： ±1°C 本地（最大），±3°C 遠(yuǎn)程（最大）
拓?fù)洌?/td> ADC，緩沖器，寄存器庫(kù)
輸出類型： I²C?/SMBus?
輸出警報(bào)： 是
輸出風(fēng)扇： 是
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
Alarm Threshold Registers
There are seven alarm threshold registers that store
overtemperature ALERT and OVERT threshold values.
Five of these registers are dedicated to store one local
alert temperature threshold limit and four remote alert
temperature threshold limits (see the ALERT Interrupt
Mode section). The remaining two registers are dedi-
cated to remote channels 1 and 4 to store overtemper-
ature threshold limits (see the OVERT Overtemperature
Alarm section). Access to these registers is provided
through the SMBus interface.
ALERT Interrupt Mode
An ALERT interrupt occurs when the internal or external
temperature reading exceeds a high-temperature limit
(user programmable). The ALERT interrupt output signal
can be cleared by reading the status register(s) associ-
ated with the fault(s) or by successfully responding to an
alert response address transmission by the master. In
both cases, the alert is cleared but is reasserted at the
end of the next conversion if the fault condition still
exists. The interrupt does not halt automatic conversions.
The ALERT output is open drain so that multiple devices
can share a common interrupt line. All ALERT interrupts
can be masked using the configuration 3 register. The
POR state of these registers is shown in Table 1.
Five-Channel Precision Temperature Monitor
_______________________________________________________________________________________   9
SMBCLK
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
A
B
C
D
E    F
G
H
I
J
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
SU:STO
t
BUF
L
M
K
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 3. SMBus Write Timing Diagram
SMBCLK
A
B
C
D
E   F
G
H
I   J   K
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 4. SMBus Read Timing Diagram
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