![](http://datasheet.mmic.net.cn/370000/MAX6441UTA_datasheet_16714298/MAX6441UTA_9.png)
M
Low-Power, Single-/Dual-Level Battery Monitors
with Hysteresis and Integrated μP Reset
_______________________________________________________________________________________
9
LBO
LTH
HTH
V
BATT
t
LBOP
t
LBOD
t
LBOP
Figure 2. Single Low-Battery Output Timing
MR
GND
RESET
t
RP
t
MRP
GND
t
MRP
t
DEB
t
MPW
t
MPW
t
DEB
SWITCH
BOUNCE
SWITCH
BOUNCE
SWITCH
BOUNCE
SWITCH
BOUNCE
V
TH
V
CC
GND
Figure 4.
RESET
Timing Diagram
LBOL
LBOH
LTH-
LTH+
HTH-
HTH+
V
BATT
t
LBOP
t
LBOP
t
D
t
LBOP
t
LBOP
LBOLH
t
D
Figure 3. Dual Low-Battery Output Timing