參數(shù)資料
型號: MAX6439UTLRYD7-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Real Time Clock/Calendar with I2C Bus™ and EEPROM; Temperature Range: -40°C to 85°C; Package: 14-TSSOP
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封裝: SOT-23, 6 PIN
文件頁數(shù): 4/14頁
文件大?。?/td> 235K
代理商: MAX6439UTLRYD7-T
M
Low-Power, Single-/Dual-Level Battery Monitors
with Hysteresis and Integrated μP Reset
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
BATT
= 1.2V to 5.5V, V
CC
= 1.2V to 5.5V, T
A
= -40
°
C to +85
°
C, unless otherwise specified. Typical values are at T
A
= +25
°
C.) (Note1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LBO
,
LBOL
,
LBOH
,
LBOLH
Timeout Period
t
LBOP
V
BATT
rising above threshold
150
225
300
ms
LBO
,
LBOL
,
LBOH
,
LBOLH
Delay Time
t
LBOD
V
BATT
falling below threshold
100
μs
(V
BATT
or V
CC
)
1.2V, I
SINK
= 50μA,
asserted low
0.3
(V
BATT
or V
CC
)
1.6V, I
SINK
= 100μA,
asserted low
0.3
(V
BATT
or V
CC
)
2.7V, I
SINK
= 1.2mA,
asserted low
0.3
LBO
,
LBOL
,
LBOH
,
LBOLH
Output Low
(Open Drain)
V
OL
(V
BATT
or V
CC
)
4.5V, I
SINK
= 3.2mA,
asserted low
0.3
V
LBO
,
LBOL
,
LBOH
,
LBOLH
Output Open-Drain Leakage
Current
I
LKG
Output deasserted
500
nA
MAX64_ _ _ _ _ _ T
MAX64_ _ _ _ _ _ S
MAX64_ _ _ _ _ _ R
MAX64_ _ _ _ _ _ Z
MAX64_ _ _ _ _ _ Y
MAX64_ _ _ _ _ _ W
MAX64_ _ _ _ _ _ V
3.000
2.850
2.550
2.250
2.125
1.620
1.530
3.075
2.925
2.625
2.313
2.188
1.665
1.575
0.3
3.150
3.000
2.700
2.375
2.250
1.710
1.620
V
CC
Reset Threshold
V
TH
V
V
CC
Reset Hysteresis
%
V
CC
to
RESET
Delay
V
CC
falling at 10mV/μs from (V
TH
+ 100mV)
to (V
TH
- 100mV)
MAX64_ _ _ _ _ _ _ D3
MAX64_ _ _ _ _ _ _ D7
50
μs
150
1200
225
1800
300
2400
V
CC
to
RESET
Timeout Period
t
RP
ms
V
IL
V
IH
t
MPW
0.3 x V
CC
MR
Input Voltage
0.7 x V
CC
1
V
MR
Minimum Pulse Width
MR
Glitch Rejection
MR
to
RESET
Delay
MR
Reset Timeout Period
MR
Pullup Resistance
MR
Rising Debounce Period
μs
ns
ns
ms
ms
100
200
225
1500
225
t
MRP
150
750
150
300
2250
300
MR
to V
CC
(Note 3)
t
DEB
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