參數(shù)資料
型號(hào): MAX6431CHUS-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Low-Power Single/Dual-Level Battery Monitors with Hysteresis
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4
封裝: SOT-143, 4 PIN
文件頁數(shù): 11/13頁
文件大?。?/td> 261K
代理商: MAX6431CHUS-T
MAX6443–MAX6452
P Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________
7
Applications Information
Interrupt Before Reset
To minimize data loss and speed system recovery,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6443–
MAX6452 manual reset inputs allows the same push-
button (connected to both the processor interrupt and
the extended MR1 input, as shown in Figure 6) to con-
trol both the interrupt and hard reset functions. If the
pushbutton is closed for less than 6.72s, the processor
is only interrupted. If the system still does not respond
properly, the pushbutton (or two buttons for the dual
manual reset) can be closed for the full extended setup
period to hard reset the processor. If desired, connect
an LED to the RESET output to blink off (or on) for the
reset timeout period to signify when the pushbutton is
closed long enough for a hard reset (the same LED
might be used as the front-panel power-on display).
Smart Card Insertion/Removal
The MAX6447/MAX6448/MAX6451/MAX6452 dual manu-
al resets are useful in applications in which both an
extended and immediate setup periods are needed.
Figure 7 illustrates the insertion and removal of a smart
card. MR1 monitors a front-panel pushbutton. When
closed for 6.72s, RESET one-shot pulses low for 140ms
min. Because MR1 is internally pulled to VCC through a
50k
resistor, the front-panel switch can be connected to
MR2
RESET
t = 210ms
t < 210ms
COUNTER RESET
Figure 3. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Assertion DebouncingTiming Diagram
MR2
RESET
210ms
DEBOUNCING PERIOD
210ms
TIMEOUT PERIOD
POSITIVE EDGE
NO RESET
OUTPUT
ASSERTED
Figure 4. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Deassertion Debouncing Timing Diagram
MAX6449
MAX6451
RSTIN
VCC
R1
R2
RESET
GND
VMON_TH = 0.63 x (R1 + R2) / R2
VMON_TH
VCC
Figure 5. Calculating the Monitored Threshold Voltages
MAX6443
P
VCC
RESET
VCC
+3.3V
NMI
LED
RESET
MR1
GND
PUSHBUTTON SWITCH:
CLOSE FOR < 4.48s
FOR SYSTEM INTERRUPT;
CLOSE FOR > 6.72s FOR
SYSTEM RESET
Figure 6. Interrupt Before Reset Application Circuit
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