• 參數(shù)資料
    型號: MAX6323FUT46-T
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: 電源管理
    英文描述: Analog IC
    中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6
    封裝: ROHS COMPLIANT, SOT-23, 6 PIN
    文件頁數(shù): 12/13頁
    文件大?。?/td> 168K
    代理商: MAX6323FUT46-T
    MAX6323/MAX6324
    falls below the preset threshold or when the manual
    reset input (MR) is asserted. The RESET output remains
    asserted for at least 100ms after VCC has risen above
    the reset threshold and MR is deasserted (Figure 5).
    For noisy environments, bybass VCC with a 500pF (min)
    capacitor to ensure correct operation.
    The MAX6323 has a push-pull output stage, and the
    MAX6324 utilizes an open-drain output. Connect a pull-
    up resistor on the RESET output of the MAX6324 to any
    supply up to +6V. Select a resistor value large enough
    to register a logic low (see
    Electrical Characteristics)
    and small enough to register a logic high while supply-
    ing all input leakage currents and leakage paths con-
    nected to the RESET line. A 10k
    pullup is sufficient in
    most applications.
    Manual Reset Input
    Many P-based products require manual reset capabil-
    ity to allow an operator or external logic circuitry to initi-
    ate a reset. The manual reset input (MR) can connect
    directly to a switch without an external pullup resistor or
    debouncing network. MR is internally pulled up to VCC
    and, therefore, can be left unconnected if unused. MR
    is designed to reject fast, negative-going transients
    (typically 100ns pulses), and it must be held low for a
    minimum of 1s to assert the reset output (Figure 5). A
    0.1F capacitor from MR to ground provides additional
    noise immunity. After MR transitions from low to high,
    reset will remain asserted for the duration of the reset
    timeout period, at least 100ms.
    Applications Information
    Negative-Going VCC Transients
    The MAX6323/MAX6324 are relatively immune to short-
    duration negative-going VCC transients (glitches),
    which usually do not require the entire system to shut
    down. Typically, 200ns large-amplitude pulses (from
    ground to VCC) on the supply will not cause a reset.
    Lower amplitude pulses result in greater immunity.
    Typically, a VCC transient that falls 100mV below the
    reset threshold and lasts less than 20s will not trigger
    a reset (see
    Typical Operating Characteristics). An
    optional 0.1F bypass capacitor mounted close to VCC
    provides additional transient immunity.
    Ensuring a Valid Reset Output
    Down to VCC = 0V
    When VCC falls below +1.2V, the MAX6323 RESET out-
    put no longer sinks current; it becomes an open circuit.
    Therefore, high-impedance CMOS logic inputs con-
    nected to RESET can drift to undetermined voltages.
    This does not present a problem in most applications,
    since most Ps and other circuitry are inoperative with
    VCC below +1.2V. However, in applications where
    RESET must be valid down to 0, adding a pulldown
    resistor to RESET causes any stray leakage currents to
    flow to ground, holding RESET low (Figure 6). R1’s
    value is not critical; 100k
    is large enough not to load
    RESET and small enough to pull RESET to ground. This
    scheme does not work with the open-drain output of the
    MAX6324.
    P Supervisory Circuits with Windowed
    (Min/Max) Watchdog and Manual Reset
    8
    _______________________________________________________________________________________
    MR
    RESET
    VCC
    VTH
    100ms (min)
    120ns (typ)
    20
    s (typ)
    1
    s (min)
    100ms (min)
    Figure 5. RESET Timing Relationship
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