參數(shù)資料
型號: MAX5965BUAX+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet; Package: SSOP;36 pin;163 mm² ; Temperature: 0°C to +85°C
中文描述: 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36
封裝: ROHS COMPLIANT, SSOP-36
文件頁數(shù): 51/54頁
文件大小: 1525K
代理商: MAX5965BUAX+
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS/OUTPUTS (Referred to DGND)
Digital Input Low
VIL
0.9
V
Digital Input High
VIH
2.4
V
Internal Input Pullup/Pulldown
Resistor
RDIN
Pullup (pulldown) resistor to VDD (DGND) to
set default level
25
50
75
k
Open-Drain Output Low VoltageVOL
ISINK = 15mA
0.4
V
Digital Input Leakage
IDL
Input connected to the pull voltage
2
A
Open-Drain Leakage
IOL
Open-drain high impedance, VOUT_ = 3.3V
2
A
TIMING
Startup Time
tSTART
Time during which a current limit set by
VSU_LIM is allowed, starts when the GATE_ is
turned on (Note 9)
50
60
70
ms
Fault Time
tFAULT
Maximum allowed time for an overcurrent
condition set by VFLT_LIM after startup
(Note 9)
50
60
70
ms
Port Turn-Off Time
tOFF
Minimum delay between any port turning off,
does not apply in case of a reset
0.5
ms
Detection Reset Time
Time allowed for the port voltage to reset
before detection starts
80
90
ms
Detection Time
tDET
Maximum time allowed before detection is
completed
330
ms
Midspan Mode Detection Delay
tDMID
2.0
2.4
s
Classification Time
tCLASS
Time allowed for classification
19
23
ms
VEEUVLO Turn-On Delay
tDLY
Time VAGND must be above the VEEUVLO
thresholds before the device operates
24
ms
RSTR bits = 00
16 x
tFAULT
RSTR bits = 01
32 x
tFAULT
RSTR bits = 10
64 x
tFAULT
Restart Timer
tRESTART
Time a port has to wait
before turning on after an
overcurrent fault during
normal operation,
RSTR_EN bits = high
RSTR bits = 11
0
ms
Watchdog Clock Period
tWD
Rate of decrement of the watchdog timer
164
ms
ADC PERFORMANCE
Resolution
9
Bits
Range
0.51
V
LSB Step Size
1mV
Integral Nonlinearity (Relative)
INL
0.2
1.5
LSB
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