參數(shù)資料
型號(hào)： MAX5963UTL+T
廠商： Maxim Integrated
文件頁數(shù)： 4/20頁
文件大?。?/td> 291K
描述： IC HOT SWAP DIO ORING CTL 40TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： FireWire? 應(yīng)用程序
內(nèi)部開關(guān)： 無
電源電壓： 7.5 V ~ 76 V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-TQFN-EP（6x6）
包裝： 帶卷 (TR)
Dual, 7.5V to 76V, Hot-Swap and
Diode ORing Controller
4  _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
PS
= V
PWR
= 12V, V
FOSO
= 0, V
ENX
= V
ENY
= V
ENZ
= V
PWR
, and T
A
= T
J
= 0癈 to +85癈, unless otherwise noted. See the Typical
Operating Circuit for connections. Typical values are at T
A
= +25癈.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ORing Threshold Comparator
Offset Voltage
7.5V d V
PWR
 d 76V, V
PS
 = V
PWR
 (Note 3)
-0.4
0
+0.4
mV
ORing Threshold Comparator
Total Offset Voltage Supply Drift
7.5V d V
PWR
 d 76V, V
PS
 = V
PWR
100
礦
ORing Threshold Comparator
Total Offset Temperature Drift
0癈 d T
A
 d +85癈, V
PS
 = V
PWR
40
礦
Fast Pulldown Current-Limit
Threshold Voltage
V
THF
7.5V d V
PWR
 d 76V, V
PS
 = V
PWR
V
CL
 +
57
mV
TIMING
Circuit-Breaker Timeout
t
CB
R
TCB
 = 4k& (Note 4)
0.85
1.02
1.23
ms
Circuit-Breaker Default Timeout
V
TCB
 = V
BP
2.2
3.0
3.8
ms
Circuit-Breaker Timeout Count-
Down/Count-Up Ratio
1
Current-Limit Timeout
t
CL
R
TCL
 = 4k& (Note 4)
0.85
1.02
1.23
ms
Current-Limit Default Timeout
V
TCL
 = V
BP
0.85
1.02
1.23
ms
Current-Limit Timeout Count-
Down/Count-Up Ratio
128
Automatic Restart Delay after
Current-Limit Timeout
t
OFFCL
t
CL
 x
128
ms
Automatic Restart Delay after
Circuit-Breaker Timeout
t
OFFCB
t
CB
 x
128
ms
Channel A/Channel B FOSO
Turn-On Delay
t
FOSOF
V
ONA
 = V
ONB
 = 3V, FOSO falling
0.4
1.0
1.5
s
ON_ Turn-On Response Time
(Time from ON_ Pulled High to
GATE_ Pulled High)
t
ON_
2
ms
ON_ Turn-Off Response Time
(Time from ON_ Pulled Low to
GATE_ Pulled Low)
t
ON_OFF
V
ON_
 < V
ONTH_HYST
, (V
GATE_
 - V
OUT
_)
< 1V, GATE_A and GATE_B are open
10
祍
FOSO Turn-Off Response Time
(Time from FOSO Rising Edge
to GATE_ Pulled Low)
t
FOSO_OFF
(V
GATE_A
 - V
OUTA
) < 1V, (V
GATE_B
 - V
OUTB
)
< 1V, GATE_A and GATE_B are open
0.34
0.60
祍
Minimum Delay from ENZ Low
to Low-Current Shutdown Mode
t
SHDN
ENZ steps from 1.3V to 0.4V
50
祍
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