參數(shù)資料
型號(hào): MAX5948BESA+T
廠商: Maxim Integrated
文件頁(yè)數(shù): 7/18頁(yè)
文件大?。?/td> 182K
描述: IC CNTRLR HOT SWAP 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開(kāi)關(guān): 無(wú)
電源電壓: -20 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
-48V Hot-Swap Controllers
with External R
SENSE
_______________________________________________________________________________________   7
Detailed Description
The MAX5948A/MAX5948B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the boards power
module or switching power supply can draw large
inrush currents as they charge. The inrush currents can
cause glitches on the system power-supply rail and
damage components on the board.
The MAX5948A/MAX5948B provide a controlled turn-on
to circuit cards preventing glitches on the power-sup-
ply rail and damage to board connectors and compo-
nents. Both the MAX5948A and MAX5948B provide
undervoltage, overvoltage, and overcurrent protection.
The MAX5948A/MAX5948B ensure the input voltage is
stable and within tolerance before applying power to
the load.
Board Insertion
Figure 6a shows a typical hot-swap circuit for -48V sys-
tems. When the circuit board first makes contact with the
backplane, the DRAIN to GATE capacitance (C
gd
) of Q1
pulls up the GATE voltage to roughly I(V
EE
x C
gd
) /
(C
gd
+ C
gs
)I. The MAX5948_ features an internal
dynamic clamp between GATE and V
EE
to keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal clamp
between GATE and V
EE
of the MAX5948A/MAX5948B
eliminates the need for an external gate-to-source
capacitor. Resistor R3 limits the current into the clamp
circuitry during card insertion.
Pin Description
PIN
MAX5948A  MAX5948B
NAME
FUNCTION
1

PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to V
EE
. PWRGD is low when V
DRAIN
 - V
EE
 d V
PG
, indicating a power-good condition.
PWRGD is open drain otherwise.

1
PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD is in a high-impedance state when V
DRAIN
 - V
EE
 d V
PG
, indicating a
power-good condition. PWRGD is pulled low to DRAIN otherwise.
2
2
OV
Input Pin for Overvoltage Detection. OV is referenced to V
EE
. When OV is pulled above
V
OVH
 voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to V
OVL
.
3
3
UV
Input Pin for Undervoltage Detection. UV is referenced to V
EE
. When UV is pulled above
V
UVH
 voltage, the GATE is enabled. When UV is pulled below V
UVL
, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below V
UVL
.
4
4
V
EE
Device Negative Power-Supply Input. Connect to the negative power-supply rail.
5
5
SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to V
EE
 to disable the circuit-
breaker feature.
6
6
GATE
Gate-Drive Output. Connect to gate of the external n-channel MOSFET.
7
7
DRAIN
Output-Voltage Sense Input. Connect to the output-voltage node (drain of external
n-channel MOSFET).
8
8
V
DD
Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the most positive potential of the power-supply inputs.
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