參數(shù)資料
型號: MAX5941B
廠商: Maxim Integrated Products, Inc.
英文描述: IEEE 802.3af-Compliant Power-Over-Ethernet Interface/PWM Controller for Power Devices
中文描述: 符合IEEE 802.3af標(biāo)準(zhǔn)的以太網(wǎng)供電接口/PWM控制器,適用于用電設(shè)備
文件頁數(shù): 10/24頁
文件大?。?/td> 453K
代理商: MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
10
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M
Pin Description
PIN
NAME
FUNCTION
1
V+
H g h- V ol ag e S ar up Inp ut. Refer enced to V C onnect d ectl y to an i np ut vol ag e r ang e b etw een 18V to 67V
C onnects i nter nal y to a hi g h- vol ag e l near r eg ul ator that g ener ates V
C C
d ur ng star up Ti e V + to GN D
2
V
DD
Line Regulator Input. Referenced to V-. V
DD
is the input to the linear regulator that generates V
CC
. For
supply voltages less than 36V, connect V
DD
and V+ to the supply. For supply voltages greater than 36V,
V
DD
receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
Bypass V
DD
to V- with a 4.7μF capacitor.
3
OPTO
Optocoupler Input. Referenced to V-. The control voltage range on this input is 2V to 3V.
4
SS_
SHDN
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
capacitor. Disable the PWM controller by pulling SS_
SHDN
below 0.25V. Tie to PGOOD to enable PWM
controller automatically from the PD interface.
5
UVLO
Undervoltage Lockout Programming Input for Power Mode. Referenced to V
EE
. When UVLO is above its
threshold, the device enters the power mode. Connect UVLO to V
EE
to use the default undervoltage lockout
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5k
(±1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between V
TH,G,UVLO
and V
REF,UVLO
.
6
RCL
C assi i cati on S etti ng Refer enced to V
E E
. Ad d a r esi stor fr om RC L to V
E E
to set a P D cl ass ( see Tab es 1 and 2)
7
GATE
Gate of Internal N-Channel Power MOSFET. Referenced to V
EE .
GATE sources 10μA when the device
enters the power mode. Connect an external 100V ceramic capacitor from GATE to V
OUT
to program the
inrush current. Pull GATE to V
EE
to turn off the internal MOSFET. The detection and classification functions
operate normally when GATE is pulled to V
EE
.
8
V
EE
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect V
EE
to -48V.
Output Voltage. Referenced to V
EE
. Drain of the integrated isolation N-channel power MOSFET. Connect
OUT to V-.
9
OUT
10
PGOOD
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
impedance when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
. Otherwise, PGOOD is pulled
to OUT (given that V
OUT
is at least 5V below GND). Connect PGOOD directly (no external pullup required)
to SS_
SHDN
to enable/disable the PWM controller.
11
PGOOD
Power-Good Indicator Output, Active Low, Open Drain.
PGOOD
is referenced to V
EE
.
PGOOD
is pulled to
V
EE
when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
. Otherwise,
PGOOD
goes high
impedance.
12
GND
Ground. Referenced to V
EE
. GND is the positive input power. Connect to V+.
13
CS
Current-Sense Input. Referenced to V-. Turns power switch off if V
CS
rises above 465mV for cycle-by-cycle
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
14
15
V-
V- is the ground terminal of the PWM Controller. Connect to GND.
Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
NDRV
16
V
CC
Regulated IC Supply. Referenced to V-. Provides power for MAX5941_. V
CC
is regulated from V
DD
during
normal operation and from V+ during startup. Bypass V
CC
with a 10μF tantalum capacitor in parallel with a
0.1μF ceramic capacitor to V-.
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