參數(shù)資料
型號： MAX5894EGK+TD
廠商： Maxim Integrated Products
文件頁數(shù)： 10/32頁
文件大?。?/td> 0K
描述： IC DAC 14BIT DUAL 500MSPS 68-QFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 886mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 500M
MAX5894
tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically re-establishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
DATACLK Modes
The MAX5894 has a main DATACLK available at
pin 14. An alternate DATACLK is available at pin 27
(DATACLK/B12) when configured in single-port data
input mode (bit 5, address 02h). The DATACLK can be
configured to accept an input clock signal for latching
the input data, or to source a clock signal that can drive
up to 10pF load while latching the input data (bit 3,
address 02h). If DATACLK is configured as an output, it
is frequency divided from the CLKP/CLKN input,
depending on the operating mode, see Table 4.
The MAX5894 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input-data bus with latching on the rising edge.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
18
______________________________________________________________________________________
INPUT
MODE
INTERPOLATION
RATE
fDATA:fCLK
fDAC:fCLK
1x
1:1
1:2
2x
1:1
4x
1:2
1:1
Single
Port
8x
1:4
1:1
1x
1:1
2x
1:2
1:1
4x
1:4
1:1
Dual Port
8x
1:8
1:1
Table 4. Clock Frequency Ratios in
Various Modes
Figure 4. Data-Input Timing Diagram
tD
tDS
tCLK
CLKP–CLKN
DATACLK
A0–A13/B0–B13
tDH
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參數(shù)描述
MAX5894EVCMOD2 功能描述:數(shù)模轉(zhuǎn)換器- DAC Evaluation Kit for the MAX5893/MAX5894/MAX5895 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5894EVKIT 功能描述:數(shù)模轉(zhuǎn)換器- DAC Evaluation Kit for the MAX5893/MAX5894/MAX5895 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5895EGK+D 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit 2Ch 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5895EGK+TD 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit 2Ch 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5895EGK-D 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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