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參數(shù)資料
| 型號： | MAX5858ECM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 300MSPS 48TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 設置時間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 816mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 300M |
MAX5858
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
12
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
10
DA2/G0
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
11
DA1
Channel A Input Data Bit 1
12
DA0
Channel A Input Data Bit 0 (LSB)
13
DB9
Channel B Input Data Bit 9 (MSB)
14
DB8
Channel B Input Data Bit 8
15
DB7
Channel B Input Data Bit 7
16
DB6
Channel B Input Data Bit 6
17
DB5
Channel B Input Data Bit 5
20
CLK
Clock Output
21
IDE
Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A
(bits DA9–DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B
is latched on the falling edge of CLK.
22
DB4
Channel B Input Data Bit 4
23
DB3
Channel B Input Data Bit 3
24
DB2
Channel B Input Data Bit 2
25
DB1
Channel B Input Data Bit 1
26
DB0
Channel B Input Data Bit 0 (LSB)
27
CW
Active-Low Control Word Write Pulse. The control word is latched on the falling edge of
CW.
28, 34
I.C.
Internally Connected. Do not connect.
29, 33
CGND
Clock Ground
30
CLKXP
Differential Clock Input Positive Terminal. Bypass CLKXP with a 0.01F capacitor to CGND when
CLKXN is in single-ended mode.
31
CLKXN
Differential Clock Input Negative Terminal. Bypass CLKXN with a 0.01F capacitor to CGND when
CLKXP is in single-ended mode.
32
CVDD
Clock Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section.
35
REN
Active-Low Reference Enable. Connect
REN to AGND to activate the on-chip 1.24V reference.
36
REFO
Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor.
37, 38
N.C.
No Connection. Not internally connected.
39
REFR
Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
between REFR and AGND. The output full-scale current is equal to 32
× VREFO/RSET.
40, 46
AVDD
Analog Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section.
41
OUTNB
Channel B Negative Analog Current Output
42
OUTPB
Channel B Positive Analog Current Output
43
AGND
Analog Ground
44
OUTNA
Channel A Negative Analog Current Output
45
OUTPA
Channel A Positive Analog Current Output
—
EP
Exposed Pad. Connect to the ground plane.
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