- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2011 > MAX5858ECM+D (Maxim Integrated Products)IC DAC 10BIT DUAL 300MSPS 48TQFP PDF資料下載
參數(shù)資料
| 型號： | MAX5858ECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 300MSPS 48TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 設置時間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 816mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 300M |
MAX5858
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
______________________________________________________________________________________
21
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec-
tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa-
gation delay and data skew mismatch.
The MAX5858 includes three separate power-supply
inputs: analog (AVDD), digital (DVDD), and clock
(CVDD). Use a single linear regulator power source to
branch out to three separate power-supply lines (AVDD,
DVDD, CVDD) and returns (AGND, DGND, CGND).
Filter each power-supply line to the respective return
line using LC filters comprising ferrite beads and 10F
capacitors. Filter each supply input locally with 0.1F
ceramic capacitors to the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage differ-
ence between DVDD, AVDD, and CVDD does not
exceed 150mV.
Thermal Characteristics and Packaging
Thermal Resistance
48-lead TQFP-EP:
θJA = 37°C/W
Keep the device junction temperature below +125°C to
meet specified electrical performance. Lower the
power-supply voltage to maintain specified perfor-
mance when the DAC update rate approaches
300Msps and the ambient temperature equals +85°C.
The MAX5858 is packaged in a 48-pin TQFP-EP pack-
age, providing greater design flexibility, increased ther-
mal efficiency, and optimized AC performance of the
DAC. The EP enables the implementation of grounding
techniques, which are necessary to ensure highest per-
formance operation.
In this package, the data converter die is attached to
an EP leadframe with the back of this frame exposed at
the package bottom surface, facing the PC board side
of the package. This allows a solid attachment of the
package to the PC board with standard infrared (IR)-
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP (5mm
5mm), ensures the proper attachment and grounding
of the DAC. Designing vias* into the land area and
implementing large ground planes in the PC board
design will allow for highest performance operation of
the DAC. Use an array of 3 3 (or greater) vias
(
≤0.3mm diameter per via hole and 1.2mm pitch
between via holes) for this 48-pin TQFP-EP package.
Dynamic Performance Parameter
Definitions
Adjacent Channel Leakage Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of all essential harmon-
ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
where V1 is the fundamental amplitude, and V2 through
VN are the amplitudes of the 2nd through Nth order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usu-
ally measured in dBc with respect to the carrier fre-
quency amplitude or in dB FS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR
is observed within a predefined window or to Nyquist.
Multitone Power Ratio (MTPR)
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per-
formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
THD
V
VN
V
=×
+
()
log
... ...
/
20
234
1
222
2
*Vias connect the land pattern to internal or external copper planes.
相關PDF資料 |
PDF描述 |
|---|---|
| MAX5863ETM+T | IC AFE 8/10BIT 7.5MSPS 48-TQFN |
| MAX5864ETM+T | IC ANLG FRONT END 22MSPS 48-TQFN |
| MAX5865ETM+T | IC ANLG FRONT END 40MSPS 48-TQFN |
| MAX5866ETM+ | IC ANLG FRONT END 60MSPS 48-TQFN |
| MAX5873EGK+D | IC DAC 12BIT 200MSPS DUAL 68-QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5858ECM-TD | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5858EVKIT | 制造商:Maxim Integrated Products 功能描述:DUAL-10-BIT, 300MSPS, CURRENT-OUTPUT DAC WITH - Bulk |
| MAX5859AEXW+D | 制造商:Maxim Integrated Products 功能描述:IC, DGTL--COM XCVR - Bulk |
| MAX5859EVKIT | 制造商:Maxim Integrated Products 功能描述:16 PINS TSSOP PKG - Bulk |
| MAX5859EVKIT-W | 制造商:Maxim Integrated Products 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。