參數資料
型號: MAX5858
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
中文描述: 雙路、10位、300Msps、電流輸出DAC,帶有4倍/2倍/1倍插值濾波器
文件頁數: 14/23頁
文件大?。?/td> 809K
代理商: MAX5858
M
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
14
______________________________________________________________________________________
Device Power-Up and
States of Operation
At power-up, the MAX5858
s default configuration is
no-interpolation mode with a gain of 0dB and a fully
operational converter. In shutdown, the MAX5858 con-
sumes only 1μA of supply current, and in standby the
current consumption is 4.4mA. Wake-up time from
standby mode to normal operation is 0.7μs.
Interpolation Filters
The MAX5858 features a two stage, 2x digital interpo-
lating filter based on 43-tap and 23-tap FIR topology.
F1EN and F2EN enable the interpolation filters. F1EN
high enables the first filter for 2x interpolation and F2EN
high enables the second filter for combined 4x interpo-
lation. To bypass and disable both interpolation filters
(no-interpolation mode or 1x mode) set F1EN = F2EN =
0. When set for 1x mode the filters are powered down
and consume virtually no current. An illegal condition is
defined by: F1EN = 0, F2EN = 1 (see Table 2 for con-
figuration modes).
The programmable interpolation filters multiply the
MAX5858 input data rate by a factor of 2x or 4x to sep-
arate the reconstructed waveform spectrum and the
first image. The original spectral images, appearing
around multiples of the DAC input data rate, are attenu-
ated at least 60dB by the internal digital filters. This fea-
ture provides three benefits:
1)
Image separation reduces complexity of analog
reconstruction filters.
2)
Lower input data rates eliminate board level high-
speed data transmission.
3)
Sin(x)/x roll-off is reduced over the effective band-
width.
Figure 2 shows an application circuit and Figure 3 illus-
trates a practical example of the benefits when using
the MAX5858 in 4x-interpolation mode. The example
illustrates signal synthesis of a 20MHz IF with a
±10MHz bandwidth. The designer can consider three
options to address the design challenge. The tradeoffs
for each solution are depicted in Table 4.
CONTROL WORD
PD
DACEN
FUNCTION
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
F2EN
Filter Enable. When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation
mode is determined by F1EN.
F1EN
Filter Enable. When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the
interpolation is disabled.
G3
G2
G1
G0
Bit 3 (MSB) of Gain Adjust Word.
Bit 2 of Gain Adjust Word.
Bit 1 of Gain Adjust Word.
Bit 0 (LSB) of Gain Adjust Word.
Table 1. Control Word Format and Function
MODE
PD
0
0
0
0
1
0
DACEN
1
1
1
0
X
1
F2EN
0
0
1
X
X
X
F1EN
0
1
1
X
X
X
No interpolation
2x interpolation
4x interpolation
Standby
Power-down
Power-up
X = Don
t care.
F1EN = 0, F2EN = 1 illegal.
Table 2. Configuration Modes
GAIN ADJUSTMENT ON
CHANNEL A (dB)
G3
G2
G1
G0
+0.4
0
-0.35
0
1
1
0
0
1
0
0
1
0
0
1
Table 3. Gain Difference Setting
MSB
PD
LSB
X
DACEN
F2EN
F1EN
G3
G2
G1
G0
X
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