參數(shù)資料
型號： MAX5732AETN
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
中文描述： SERIAL INPUT LOADING, 20 us SETTLING TIME, 16-BIT DAC, QCC56
封裝： 8 X 8 MM, 0.80 MM HEIGHT, MO-220, QFN-56
文件頁數(shù)： 10/26頁
文件大?。?/td> 451K
代理商： MAX5732AETN
M
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
10
______________________________________________________________________________________
TIMING CHARACTERISTICS—DV
DD
= +2.7V to +5.25V
(Figures 2 and 3, AV
DD
= +4.75V to +5.25V, DV
DD
= +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
SCS
t
CSS
t
CS1
t
CS2
t
DS
t
DH
t
SCL
t
SDH
t
CSPWH
t
CSPWL
t
LDAC
t
CLR
CONDITIONS
MIN
0
10
10
10
10
18
0
10
2
TYP
MAX
25
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to
CS
Fall Setup Time
CS
Fall to SCLK Fall Setup Time
CS
Rise to SCLK Fall
SCLK Fall to
CS
Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS
Pulse-Width High
CS
Pulse-Width Low
LDAC
Pulse-Width Low
CLR
Pulse-Width Low
At end of cycle in SPI mode only
Load capacitance = 20pF
Load capacitance = 20pF
25
25
50
20
20
20
TIMING CHARACTERISTICS—DV
DD
= +4.75V to +5.25V
(Figures 2 and 3, AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
SCS
t
CSS
t
CS1
t
CS2
t
DS
t
DH
t
SCL
t
SDH
t
CSPWH
t
CSPWL
t
LDAC
t
CLR
CONDITIONS
MIN
0
10
10
6
5
15
0
10
2
TYP
MAX
33
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to
CS
Fall Setup Time
CS
Fall to SCLK Fall Setup Time
CS
Rise to SCLK Fall
SCLK Fall to
CS
Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS
Pulse-Width High
CS
Pulse-Width Low
LDAC
Pulse-Width Low
CLR
Pulse-Width Low
At end of cycle in SPI mode only
Load capacitance = 20pF
Load capacitance = 20pF
20
20
50
20
20
20
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