參數(shù)資料
型號： MAX5632
廠商： Maxim Integrated Products, Inc.
英文描述： 16-Bit DACs with 32-Channel Sample-and-Hold Outputs
中文描述： 16位DAC，帶有32通道采樣/保持輸出
文件頁數(shù)： 3/16頁
文件大小： 667K
代理商： MAX5632
M
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, AGND = DGND = V
GS
= 0, R
L
≥
10M
, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
SCLK Feedthrough
f
SEQ
Feedthrough
Hold-Step
Droop Rate
Output Noise
REFERENCE INPUT
Input Resistance
Reference Input Voltage
GROUND-SENSE INPUT
Input Voltage Range
Input Bias Current
GS Gain
DIGITAL INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
TIMING CHARACTERISTICS
(FIGURE 2)
Sequencer Clock Frequency
External Clock Frequency
SCLK Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
(Note 4)
0.08
%
0.5
0.5
0.25
1
250
nV-s
nV-s
mV
mV/s
μV
RMS
1
40
V
OUT_
= 0 (Note 5), T
A
= +25
°
C
7
k
V
V
REF
2.5
V
GS
I
GS
-0.5
-60
0.998
0.5
0
1.002
V
-0.5V
≤
V
GS
≤
0.5V
(Note 6)
μA
V/V
1
V
IH
V
IL
2.0
V
V
0.8
±
1
μA
f
SEQ
f
ECLK
f
SCLK
t
CH
t
CL
Internal oscillator
(Note 7)
80
100
120
480
20
kHz
kHz
MHz
ns
ns
15
15
CS
Low to SCLK High Setup
Time
t
CSSO
15
ns
CS
High to SCLK High Setup
Time
t
CSS1
15
ns
SCLK High to
CS
Low Hold Time
t
CSH0
10
ns
相關PDF資料
PDF描述
MAX561 3.3V Transceiver with Two EIA TIA 562 Receivers Active in Shutdown
MAX5622 16-Bit DACs with 16-Channel Sample-and-Hold Outputs
MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs
MAX5633 16-Bit DACs with 32-Channel Sample-and-Hold Outputs
MAX563CPN +3.3V-Powered, EIA/TIA-562 Dual Transceiver with Receivers Active in Shutdown
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