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參數(shù)資料
| 型號： | MAX5622 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 16-Bit DACs with 16-Channel Sample-and-Hold Outputs |
| 中文描述： | 16位DAC，帶有16通道采樣/保持輸出 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 667K |
| 代理商： | MAX5622 |
M
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
4
_______________________________________________________________________________________
Note 1:
The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when V
SS
< -4.9V, and the nominal full-scale voltage may be achieved when V
DD
> +11.5V.
Note 2:
Gain is calculated from measurements
for voltages V
DD
= 10V and V
SS
= -4V at codes C000 hex and 4F2C hex,
for voltages V
DD
= 11.6V and V
SS
= -2.9V at codes FFFF hex and 252E hex,
for voltages V
DD
= 9.25V and V
SS
= -5.25V at codes D4F6 hex and 0 hex, and
for voltages V
DD
= 8.55V and V
SS
= -2.75V at codes C74A hex and 281C hex.
Note 3:
Steady-state change in any output with an 8V change in an adjacent output.
Note 4:
Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5:
External clock mode with the external clock not toggling.
Note 6:
The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7:
The sequencer runs at f
SEQ
= f
ECLK
/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
Note 8:
V
DD
rise to
CS
low = 500μs maximum.
Note 9:
Guaranteed by gain-error test.
Note 10:
The serial interface is inactive. V
IH
= V
LOGIC
, V
IL
= 0.
Note 11:
The serial interface is active. V
IH
= V
LOGIC
, V
IL
= 0.
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, AGND = DGND = V
GS
= 0, R
L
≥
10M
, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
t
CSH1
t
DS
t
DH
CONDITIONS
MIN
0
15
TYP
MAX
UNITS
ns
ns
ns
μs
SCLK High to
CS
High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST
to
CS
Low
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
0
(Note 8)
500
V
DD
V
SS
(Note 9)
(Note 9)
V
DD
- V
SS
(Note 9)
8.55
-5.25
10
-4
11.6
-2.75
14.5
V
V
V
Logic Supply Voltage
V
LOGIC
,
V
LDAC
,
V
LSHA
4.75
5
5.25
V
Positive Supply Current
Negative Supply Current
I
DD
I
SS
32
32
1
2
42
40
1.5
3
mA
mA
(Note 10)
f
SCLK
= 20MHz (Note 11)
Logic Supply Current
I
LOGIC
mA
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