參數(shù)資料
型號： MAX5591
廠商： Maxim Integrated Products, Inc.
元件分類： DAC
英文描述： Buffered. Fast-Settling. Octal. 12/10/8-Bit. Voltage-Output DACs
中文描述： 帶緩沖、快速建立、八通道、12/10/8位、電壓輸出DAC
文件頁數(shù)： 9/33頁
文件大?。?/td> 1114K
代理商： MAX5591
M
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________
9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD= 1.8V to 5.25V, GND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
CSS
t
DSS
t
CSH
t
CS0
t
DS0
t
DS
t
DH
CONDITIONS
MIN
TYP
MAX
10
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Fall Setup Time
DSP
Fall to SCLK Fall Setup Time
SCLK Fall to
CS
Rise Hold Time
SCLK Fall to
CS
Fall Delay
SCLK Fall to
DSP
Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
1.8V < DV
DD
< 5.25V
(Note 7)
(Note 7)
40
40
20
20
0
10
15
20
5
SCLK Rise to DOUT_ Valid
Propagation Delay
t
DO1
C
L
= 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
60
ns
SCLK Fall to DOUT_ Valid
Propagation Delay
t
DO2
C
L
= 20pF, UPIO_ = DOUTDC0 mode
60
ns
CS
Rise to SCLK Fall Hold Time
CS
Pulse-Width High
DSP
Pulse-Width High
DSP
Pulse-Width Low
UPIO_ TIMING CHARACTERISTICS
t
CS1
t
CSW
t
DSW
t
DSPWL
MICROWIRE and SPI modes 0 and 3
20
90
40
40
ns
ns
ns
ns
(Note 8)
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
t
DOZ
C
L
= 20pF, from end of write cycle to UPIO_
in high impedance
200
ns
DOUTRB Tri-State Time from
CS
Rise
t
DRBZ
C
L
= 20pF, from rising edge of
CS
to UPIO_
in high impedance
40
ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
t
ZEN
C
L
= 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
40
ns
LDAC
Pulse-Width Low
LDAC
Effective Delay
CLR
,
MID
,
SET
Pulse-Width Low
GPO Output Settling Time
t
LDL
t
LDS
t
CMS
t
GP
Figure 5
Figure 6
Figure 5
Figure 6
40
200
40
ns
ns
ns
ns
200
GPO Output High-Impedance
Time
t
GPZ
200
ns
Note 7:
In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8:
The falling edge of
DSP
starts a DSP-type bus cycle, provided that
CS
is also active low to select the device.
DSP
active low
and
CS
active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V).
CS
can be permanently low in this mode of
operation.
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