參數(shù)資料
型號： MAX5580BETP
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
中文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, QCC20
封裝： 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHC, TQFN-20
文件頁數(shù)： 30/36頁
文件大小： 1018K
代理商： MAX5580BETP
M
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
30
______________________________________________________________________________________
GPI, GPOL, GPOH
UPIO1 and UPIO2 can each be configured as a gener-
al-purpose input (GPI), a general-purpose output low
(GPOL), or a general-purpose output high (GPOH).
The GPI can serve to detect interrupts from μPs or micro-
controllers. The GPI has three functions:
1) Sample the signal at GPI at the time of the read
(RTP1 and RTP2).
2) Detect whether a falling edge has occurred since
the last read or reset (LF1 and LF2).
3) Detect whether a rising edge has occurred since
the last read or reset (LR1 and LR2).
RTP1, LF1, and LR1 represent the data read from
UPIO1; RTP2, LF2, and LR2 represent the data read
from UPIO2.
To issue a read command for the UPIO configured as
GPI, use the command in Table 22.
Once the command is issued, RTP1 and RTP2 provide
the real-time status (0 or 1) of the inputs at UPIO1 or
UPIO2, respectively, at the time of the read. If LF2 or
LF1 is one, then a falling edge has occurred on the
respective UPIO1 or UPIO2 input since the last read or
reset. If LR2 or LR1 is one, then a rising edge has
occurred since the last read or reset.
GPOL outputs a constant low, and GPOH outputs a
constant high. See Figure 6.
TOGG
Use the TOGG input to toggle the DAC outputs
between the values in the input registers and DAC reg-
isters. A delay of greater than 100ns from the end of the
previous write command is required before the TOGG
signal can be correctly switched between the new
value and the previously stored value. When TOGG =
0, the output follows the information in the input regis-
ters. When TOGG = 1, the output follows the informa-
tion in the DAC register (Figure 5).
FAST
The MAX5580–MAX5585 have two settling-time-mode
options: FAST (3μs max) and SLOW (6μs max). To
select the FAST mode, drive
FAST
low, and to select
SLOW mode, drive
FAST
high. This overrides (not over-
writes) the SPDA–SPDD bit settings.
Table 22. GPI Read Command
DATA
DIN
DOUTRB
CONTROL BITS
1
X
DATA BITS
X
LF2
1
X
1
X
1
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
RTP2
LR2
RTP1
LF1
LR1
Table 23. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB
1111
1111
1000
0000
1000
0000
0111
1111
0000
0000
0000
0000
LSB
1111
0001
0000
1111
0001
0000
ANALOG OUTPUT
+V
REF
(4095 / 4096)
+V
REF
(2049 / 4096)
+V
REF
(2048 / 4096) = V
REF
/ 2
+V
REF
(2047 / 4096)
+V
REF
(1 / 4096)
0
MAX5580
DAC_
REF
OUT_
V
= V
x CODE / 4096
WHERE CODE IS THE DAC INPUT
CODE (0 TO 4095 DECIMAL)
MAX6126
Figure 7. Unipolar Output Circuit
X = Don’t care.
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