- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8538 > MAX5556ESA+T (Maxim Integrated Products)IC DAC STEREO AUDIO 8-SOIC PDF資料下載
參數(shù)資料
| 型號： | MAX5556ESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO AUDIO 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 50k |
MAX5556
Low-Cost Stereo Audio DAC
15
Maxim Integrated
Loss of Clock and Invalid Clock Conditions
The MAX5556 mutes both outputs after detecting one
of four invalid clock conditions. The device mutes its
output to prevent propagation of pops, clicks, or cor-
rupted data through the signal path. The MAX5556
forces the outputs to the quiescent DC voltage (2.4V) to
prevent clicks in capacitive-coupled systems. Invalid
clock conditions include:
1) MCLK/LRCLK ratio changes between 256, 384,
and 512
2) Transition between internal and external serial-
clock mode
3) Invalid MCLK/LRCLK ratio
4) MCLK falls below the minimum operating
frequency 2kHz
When the MCLK/LRCLK ratio returns to 256, 384, or
512 and MCLK is equal or greater than its minimum
operating frequency, the MAX5556 output returns to its
full-scale setting over a soft-start mute time of 20ms
(Figure 12).
Power-Down
When the positive supply is removed from the
MAX5556, the output discharges to ground. When
power is restored, the power-up ramp routine engages
once a valid clock ratio is established (see the
Power-
Up section).
Avoid violating absolute maximum conditions by sup-
plying digital inputs to the part or forcing voltages on
the analog outputs during a loss-of-power event.
Applications Information
Low-Cost Line-Level Solution
Connect the MAX5556 output through a passive output
filter as detailed in Figure 8 for a low-cost solution. This
lowpass filter yields single-pole (20dB/decade) roll-off
at a corner frequency (fC) determined by:
In the case of Figure 8, fC is approximately 190kHz.
High-Performance Line-Level Solution
For enhanced performance, connect the MAX5556
output to an active filter by using an operational amplifi-
er as shown in Figure 9. The use of an active filter allows
for steeper roll-off, more efficient filtering, and also adds
the capability of a programmable output gain.
Power-Supply Sequencing
For correct power-up sequencing, apply VDD and then
connect the input digital signals. Do not apply digital sig-
nals before VDD is applied.
Do not violate any of the absolute maximum ratings by
removing power with the digital inputs still connected.
To correctly power down the device, first disconnect
the digital input signals, and then remove VDD.
Power-Supply Connections and Ground
Management
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and analog outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Route the analog
paths (GND, VDD, OUTL, and OUTR) away from the
digital signals. Connect a 0.1F capacitor in parallel
with a 4.7F capacitor as close to VDD as possible. Low
ESR-type capacitors are recommended for supply
decoupling applications. A small value C0G-type
bypass capacitor located as close to the device as
possible is recommended in parallel with larger values.
f
RC
C =
1
2
π
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX5522EUA+T | IC DAC 10BIT DUAL ULP 8-UMAX |
| MAX5139GTE+T | IC DAC V-OUT 12BIT 1CH 16-TQFN |
| MAX5511ETC+ | IC DAC 8BIT VOUT 12-TQFN-EP |
| MAX5520ETC+T | IC DAC 10BIT SGL ULP 12-TQFN |
| MAX5514ETC+ | IC DAC 8BIT DUAL VOUT 12TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5556GSA+ | 功能描述:IC DAC STEREO AUDIO 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:3,000 系列:nanoDAC™ 設(shè)置時間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應商設(shè)備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產(chǎn)品目錄頁面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR |
| MAX555CCB+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB-TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC NULL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。