參數(shù)資料
型號: MAX5532
廠商: Maxim Integrated Products, Inc.
英文描述: Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
中文描述: 雙路、超低功耗、12位、電壓輸出DAC
文件頁數(shù): 14/24頁
文件大小: 1554K
代理商: MAX5532
M
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
14
______________________________________________________________________________________
Detailed Description
The MAX5532–MAX5535 dual, 12-bit, ultra-low-power,
voltage-output DACs offer Rail-to-Rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5μA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18μA (max). The MAX5533/MAX5535 include an
internal reference that saves additional board space
and can source up to 8mA, making it functional as a
system reference. The 16MHz, 3-wire serial interface is
compatible with SPI, QSPI, and MICROWIRE protocols.
When V
DD
is applied, all DAC outputs are driven to
zero scale with virtually no output glitch. The MAX5532/
MAX5533 output buffers are configured in unity gain
and come in μMAX packages. The MAX5534/MAX5535
output buffers are configured in force sense allowing
users to externally set voltage gains on the output (an
output-amplifier inverting input is available). The
MAX5534/MAX5535 come in 4mm x 4mm thin QFN
packages.
Digital Interface
The MAX5532–MAX5535 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5532–MAX5535 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface.
CS
must remain low until all 16 bits
are clocked in. The 16 bits consist of 4 control bits
(C3–C0) and 12 data bits (D11–D0) (
Table
1). Following
the control bits, the data loads MSB first, D11–D0. The
control bits C3–C0 control the MAX5532–MAX5535, as
outlined in
Table
2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
Loading the input registers without updating the DAC
registers
Updating the DAC registers from the input registers
Updating all the input and DAC registers simultaneously
Functional Diagrams (continued)
12-BIT DAC
2-BIT
PROGRAMMABLE
REFERENCE
DAC
REGISTER
OUTA
REF
BUF
GND
MAX5535
REFOUT
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
12-BIT DAC
DAC
REGISTER
OUTB
FBA
FBB
SCLK
V
DD
DIN
CS
INPUT
REGISTER
相關(guān)PDF資料
PDF描述
MAX5532EUA Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
MAX5533 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
MAX5533EUA Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
MAX5534ETC Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
MAX5535ETC Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
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