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  • 參數(shù)資料
    型號(hào): MAX552AEPA
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: DAC
    英文描述: 12-Bit Digital-to-Analog Converter
    中文描述: SERIAL INPUT LOADING, 0.12 us SETTLING TIME, 12-BIT DAC, PDIP8
    封裝: PLASTIC, DIP-8
    文件頁(yè)數(shù): 6/16頁(yè)
    文件大?。?/td> 172K
    代理商: MAX552AEPA
    M
    +2.5V to +5.5V, Low-Power, S ingle/Dual,
    8-Bit Voltage-Output DACs in μMAX Pac kage
    6
    _______________________________________________________________________________________
    _______________Detailed Desc ription
    Analog S ec tion
    The MAX548A/MAX549A/MAX550A are 8-bit, voltage-
    output digital-to-analog converters (DACs). The
    MAX548A/MAX549A are dual DACs, and the MAX550A
    is a single DAC. Each DAC consists of an R-2R ladder
    network that converts 8-bit digital inputs into equivalent
    analog output voltages in proportion to the applied ref-
    erence voltage (Figure 1).
    The DAC s feature double-buffered inputs and
    unbuffered outputs. The MAX549A/MAX550A require
    an external reference. The MAX548A’s reference inputs
    are internally connected to V
    DD
    . The power-supply
    range is from +2.5V to +5.5V.
    Reference Input
    The voltage applied at REF (V
    DD
    for the MAX548A) sets
    the full-scale output for all the DACs and may range
    from +2.5V to V
    DD
    . The REF input resistance is code
    dependent, with the lowest value occurring with code
    01010101 (55 hex). To minimize INL errors, the refer-
    ence voltage source should have less than 3
    output
    impedance.
    DAC Output
    The MAX548A/MAX549A/MAX550A contain DACs with
    unbuffered outputs; each output connects directly to an
    R-2R ladder. Typical output impedance is 33.3k
    . This
    configuration minimizes power consumption and
    reduces offset errors. For highest accuracy, apply high
    resistive loads (1M
    and up). Lower resistive loads can
    be driven, but output loading increases full-scale error.
    The magnitude of the expected error is the ratio of the
    DAC output resistance to the DC load resistance at the
    output.
    Typically, an energy pulse is coupled into the DAC out-
    put on
    CS
    ’s rising edge. Since each DAC output is
    unbuffered, connecting a small capacitor (200pF to
    1000pF) from the output to ground creates a lowpass
    filter that effectively suppresses the pulse for sensitive
    applications (see Typical Operating Characteristics).
    Shutdown Mode
    When the MAX548A/MAX549A/MAX550A are in shut-
    down mode, the R-2R ladder disconnects from the refer-
    ence source. The MAX549A/MAX550A supply current
    does not change, but the REF input current decreases to
    less than 1μA. This allows the externally applied system
    reference to remain active with minimal power
    consumption. The MAX548A supply current also
    decreases to less than 1μA in shutdown mode. When the
    MAX548A/MAX549A/MAX550A exit shutdown mode,
    recovery time is equivalent to the DAC’s settling time.
    S erial Interfac e
    The serial interface is SPI/QSPI and Microwire compati-
    ble. An active-low chip select (
    CS
    ) enables the input
    shift register to receive data from the serial input (DIN).
    Data is clocked into the shift register on the rising edge
    of the serial-clock signal (SCLK). The clock frequency
    can be as high as 10MHz.
    Transmit data MSB first in one 16-bit word or two 8-bit
    bytes. The write cycle can be segmented to allow two
    8-bit-wide transfers when
    CS
    remains low. After all 16
    bits are clocked into the input shift register, a rising
    2R
    R
    R
    R
    R
    2R
    2R
    2R
    2R
    REF
    GND
    NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX.
    DAC_ REGISTER
    OUT_
    MSB
    LSB
    GND
    2R
    R
    R
    R
    2R
    2R
    2R
    Figure 1. DAC Simplified Circuit Diagram
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