參數(shù)資料
型號(hào)： MAX541CEPA
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： +5V, Serial-Input, Voltage-Output, 16-Bit DACs
中文描述： SERIAL INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDIP8
封裝： 0.300 INCH, PLASTIC, MS-001AB, DIP-8
文件頁(yè)數(shù)： 3/12頁(yè)
文件大小： 239K
代理商： MAX541CEPA
M
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%, V
REF
= +2.5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, V
REF
= +2.5V, AGND = DGND = 0, CMOS inputs, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
SYMBOL
PARAMETER
Note 1:
Gain Error tested at V
REF
= 2.0V, 2.5V, and 3.0V.
Note 2:
R
OUT
tolerance is typically ±20%.
Note 3:
Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4:
Reference input resistance is code dependent, minimum at 8555 hex.
Note 5:
Slew-rate value is measured from 0% to 63%.
Note 6:
Guaranteed by design. Not production tested.
Code = 0000 hex;
CS
= V
DD;
LDAC
= 0;
SCLK, DIN = 0 to V
DD
levels
Major-carry transition
V
IN
= 0
(Note 6)
Code = 0000 hex, V
REF
= 1Vp-p at 100kHz
Code = 0000 hex
Code = FFFF hex
CONDITIONS
mW
1.5
PD
Power Dissipation
mA
0.3
1.1
I
DD
Positive Supply Current
V
4.75
5.25
V
DD
Positive Supply Range
V
0.40
V
H
Hysteresis Voltage
POWER SUPPLY
pF
10
C
IN
Input Capacitance
mVp-p
dB
1
92
75
120
nVs
10
nVs
10
DAC Glitch Impulse
Digital Feedthrough
μA
±1
I
IN
Input Current
V
0.8
V
IL
Input Low Voltage
V
2.4
V
IH
Input High Voltage
Reference Feedthrough
Signal-to-Noise Ratio
SNR
pF
C
IN
Reference Input Capacitance
UNITS
MIN
TYP
MAX
MAX542 (Note 6)
MAX542
(Note 6)
CONDITIONS
μs
20
V
DD
High to
CS
Low
(power-up delay)
ns
ns
ns
ns
ns
45
45
45
30
45
t
CL
t
CSS0
t
CSS1
t
CSH0
t
CSH1
SCLK Pulse Width Low
CS
Low to SCLK High Setup
CS
High to SCLK High Setup
SCLK High to
CS
Low Hold
SCLK High to
CS
High Hold
ns
45
t
CH
MHz
10
f
CLK
SCLK Frequency
SCLK Pulse Width High
ns
50
t
LDACS
CS
High to
LDAC
Low Setup
ns
50
t
LDAC
LDAC
Pulse Width
ns
0
t
DH
DIN to SCLK High Hold
ns
40
t
DS
DIN to SCLK High Setup
UNITS
MIN
TYP
MAX
Code = FFFF hex
MHz
1
BW
Reference -3dB Bandwidth
DYNAMIC PERFORMANCE—REFERENCE SECTION
STATIC PERFORMANCE—DIGITAL INPUTS
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