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參數(shù)資料
| 型號： | MAX541 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad LVDS Transmitter 20-LCCC -55 to 125 |
| 中文描述： | +5V、串行輸入、電壓輸出16位DAC |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 239K |
| 代理商： | MAX541 |
M
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
8
_______________________________________________________________________________________
Digital Interface
The MAX541/MAX542’s digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (
CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following
CS
’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on
CS
’s low-to-high transition (Figure 3a). Note
that if
CS
is not kept low during the entire 16 SCLK
cycles, data will be corrupted. In this case, reload the
DAC latch with a new 16-bit word.
Alternatively, for the MAX542,
LDAC
allows the DAC
latch to update asynchronously by pulling
LDAC
low
after
CS
goes high (Figure 3b). Hold
LDAC
high during
the data-loading sequence.
External Reference
The MAX541/MAX542 operate with external voltage ref-
erences from 2V to 3V. The reference voltage deter-
mines the DAC’s full-scale output voltage. Kelvin
connections are provided with the MAX542 for optimum
performance.
Power-On Reset
The MAX541/MAX542 have a power-on reset circuit to
set the DAC’s output to 0V in unipolar mode when V
DD
is first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after a loss of power. In bipolar
mode, the DAC output is set to -V
REF
.
CS
SCLK
DIN
MSB
LSB
D15
D8
D7 D6 D5 D4 D3 D2
D1 D0
DAC
UPDATED
D14 D13 D12 D11 D10 D9
CS
SCLK
DIN
LDAC
MSB
LSB
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1
D0
DAC
UPDATED
Figure 3a. MAX541/MAX542 3-Wire Interface Timing Diagram (
LDAC
= DGND for MAX542)
Figure 3b. MAX542 4-Wire Interface Timing Diagram
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