參數(shù)資料
型號(hào): MAX5387MAUD+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/15頁
文件大小: 0K
描述: IC DGTL POT 256POS 50K 14TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.6 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
Dual, 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometer
MAX5387
12 _____________________________________________________________________________________
REG B: The data byte writes to register B and the wiper
of potentiometer B moves to the appropriate position.
D[7:0] indicates the position of the wiper. D[7:0] = 00h
moves the wiper to the position closest to LB. D[7:0] =
FFh moves the wiper to the position closest to HB. D[7:0]
is 80h following power-on.
REGS A and B: The data byte writes to registers A and
B and the wipers of potentiometers A and B move to
the appropriate position. D[7:0] indicates the position
of the wiper. D[7:0] = 00h moves the wipers to the posi-
tion closest to L_. D[7:0] = FFh moves the wipers to the
position closest to H_. D[7:0] is 80h following power-on.
Applications Information
Variable Gain Amplifier
Figure 8 shows a potentiometer adjusting the gain of a
noninverting amplifier. Figure 9 shows a potentiometer
adjusting the gain of an inverting amplifier.
Adjustable Dual Regulator
Figure 10 shows an adjustable dual linear regulator
using a dual potentiometer as two variable resistors.
Adjustable Voltage Reference
Figure 11 shows an adjustable voltage reference circuit
using a potentiometer as a voltage-divider.
Table 2. I2C Command Byte Summary
Figure 8. Variable Gain Noninverting Amplifier
Figure 9. Variable Gain Inverting Amplifier
Figure 10. Adjustable Dual Linear Regulator
ADDRESS BYTE
COMMAND BYTE
DATA BYTE
SCL
CYCLE NO.
START
(S)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
STOP
(P)
A6 A5 A4
A3 A2 A1
A0
W
ACK
(A)
R7 R6 R5 R4 R3
R2 R1 R0
ACK
(A)
D7 D6 D5 D4 D3 D2 D1 D0
ACK
(A)
REG A
0
1
0
1
A2 A1
A0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
REG B
0
1
0
1
A2 A1
A0
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
REGS
A AND B
0
1
0
1
A2 A1
A0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
VIN
VOUT
H
L
W
VIN
VOUT
H
L
W
VOUT1
VOUT2
OUT1
OUT2
SET1
SET2
IN
V+
L
H
W
MAX8866
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