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參數(shù)資料
型號(hào)： MAX5316GTG+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 30/33頁(yè)
文件大小： 0K
描述： IC DAC 16BIT SPI 24TQFN
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 3µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 2.29W
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-TQFN-EP（4x5）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
6
MAX5316
16-Bit, ±1 LSB Accuracy Voltage Output
DAC with SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC
= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1F, TA = -40°C to +105°C, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION
Reference High Input Range
VREF
2.4
VAVDD
- 0.1
V
Reference Input Capacitance
CREF
10
pF
Reference Input Resistance
RREF
10
MI
Reference Input Current
IB
Q
0.05
F
A
STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION
Reference High Output Range
2.4
VAVDD
- 0.1
V
Reference High Output Load
Regulation
500
ppm/mA
Reference Output Capacitor
RESR < 5I
0.1
0.15
nF
STATIC PERFORMANCE—VBYPASS OUT SECTION
Output Voltage
VBYPASS
2.3
2.4
2.5
V
Load Capacitance to GND
CL
Required for stability, RESR = 0.1I (typ)
1
10
F
POWER-SUPPLY REQUIREMENTS
Positive Analog Power-Supply
Range
VAVDD
2.7
3.3
V
Interface Power-Supply Range
VDDIO
1.7
VAVDD
V
Negative Analog Power-Supply
Range
VAVSS
-1.5
-1.25
0
V
Positive Analog Power-Supply
Current
IAVDD
No load, external reference, output at zero
scale
4
6.5
mA
Negative Analog Power-Supply
Current
IAVSS
No load, external reference, output at zero
scale
-1.5
-0.8
mA
Interface Power-Supply Current
IVDDIO
Digital inputs at VDDIO or DGND
1
10
F
A
Positive Analog Power-Supply
Power-Down Current
PD = VDDIO, power-down mode
20
50
F
A
Negative Analog Power-Supply
Power-Down Current
PD = VDDIO, power-down mode
-10
-3
F
A
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
From 10% to 90% full scale, positive and
negative transitions
4.9
V/Fs
Voltage Output Settling Time
tS
From falling edge of LDAC to within 0.003%
FS, RL = 10kI, DIN = 1000h (6.25% FS) to
F000h (93.75% FS)
3
F
s
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