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參數(shù)資料
| 型號： | MAX530ACWG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 25 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | SO-24 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | MAX530ACWG |
M
________________Detailed Description
The MAX530 consists of a parallel-input logic interface, a
12-bit R-2R ladder, a reference, and an op amp. The
Functional Diagram shows the control lines and signal
flow through the input data latch to the DAC latch, as well
as the 2.048V reference and output op amp. Total supply
current is typically 250μA with a single +5V supply. This
circuit is ideal for battery-powered, microprocessor-con-
trolled applications where high accuracy, no adjustments,
and minimum component count are key requirements.
R-2R Ladder
The MAX530 uses an “inverted” R-2R ladder network with
a BiCMOS op amp to convert 12-bit digital data to analog
voltage levels. Figure 1 shows a simplified diagram of the
R-2R DAC and op amp. Unlike a standard DAC, the
MAX530 uses an “inverted” ladder network. Normally, the
REFIN pin is the current output of a standard DAC and
would be connected to the summing junction, or virtual
ground, of an op amp. In this standard DAC configura-
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
8
_______________________________________________________________________________________
2R
2R
2R
2R
2R
R
R
R
MSB
OUTPUT
BUFFER
VOUT
RFB
ROFS
MAX530
2R
2R
REFIN
AGND
DAC LATCH
R
=
80k
LSB
NBL
INPUT
LATCH
NBH
INPUT
LATCH
NBM
INPUT
LATCH
D0/D8
D1/D9
D2/D10
D4
D3/D11
D6
D5
D7
2.048V
REFOUT
REFGND
*SHOWN FOR ALL 1s
*
LSB
MSB
CLR
Figure 1. Simplified MAX530 DAC Circuit
tion, however, the output voltage would be the inverse of
the reference voltage. The MAX530’s topology makes the
ladder output voltage the same polarity as the reference
input, which makes the device suitable for single-supply
operation. The BiCMOS op amp is then used to buffer,
invert, or amplify the ladder signal.
Ladder resistors are nominally 80k
to conserve power
and are laser trimmed for gain and linearity. The input
impedance at REFIN is code dependent. When the DAC
register is all 0s, all rungs of the ladder are grounded
and REFIN is open or no load. Maximum loading (mini-
mum REFIN impedance) occurs at code 010101... or
555hex. Minimum reference input impedance at this
code is guaranteed to be not less than 40k
.
The REFIN and REFOUT pins allow the user to choose
between driving the R-2R ladder with the on-chip refer-
ence or an external reference. REFIN may be below ana-
log ground when using dual supplies. See the External
Reference and Four-Quadrant Multiplicationsections for
more information.
Internal Referenc e
The on-chip reference is laser trimmed to generate
2.048V at REFOUT. The output stage can source and
sink current so REFOUT can settle to the correct volt-
age quickly in response to code-dependent loading
changes. Typically source current is 5mA and sink cur-
rent is 100μA.
REFOUT connects the internal reference to the R-2R
DAC ladder at REFIN. The R-2R ladder draws 50μA
maximum load current. If any other connection is made
to REFOUT, ensure that the total load current is less
than 100μA to avoid gain errors.
A separate REFGND pin is provided to isolate refer-
ence currents from other analog and digital ground
currents. To achieve specified noise performance, con-
nect a 33μF capacitor from REFOUT to REFGND (see
Figure 2). Using smaller capacitance values increases
noise, and values less than 3.3μF may compromise the
reference’s stability. For applications requiring the low-
est noise, insert a buffered RC filter between REFOUT
and REFIN. When using the internal reference,
REFGND must be connected to AGND. In applications
not requiring the internal reference, connect REFGND
to V
DD
, which shuts down the reference and saves typ-
ically 100μA of V
DD
supply current.
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| MAX530AENG | +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC |
| MAX530AEWG | +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC |
| MAX530BCAG | +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC |
| MAX530BCWG | ECONOLINE: RJ & RG - Dual Output from a Single Input Rail - 3kVDC & 4kVDC Isolation - Optional Continuous Short Circuit Protected - Custom Solutions Available - UL94V-0 Package Material - Efficiency to 84% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX530ACWG+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX530ACWG+T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX530ACWG-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX530AEAG | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX530AEAG+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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