參數(shù)資料
型號： MAX5291AETE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： LJT 21C 21#16 PIN WALL RECP
中文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, QCC16
封裝： 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGC, TQFN-16
文件頁數(shù)： 24/33頁
文件大小： 941K
代理商： MAX5291AETE
M
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
24
______________________________________________________________________________________
Table 20. UPIO Programming Example
DATA
DIN
CONTROL BITS
1
1
DATA BITS
1
1
0
1
0
0
X
0
0
0
0
0
X
X
X = Don’t care.
Table 21. UPIO Read Command
DATA
DIN
DOUTRB
CONTROL BITS
1
X
DATA BITS
X
1
X
1
X
0
X
1
X
0
X
1
X
X
X
X
X
X
X
X
X
X
UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don’t care.
and CPHA = 1 or set CPOL = 1 and CPHA = 0 for DSP
and SPI applications requiring the clocking of data in on
the falling edge of SCLK (refer to the
Programmer’s
Handbook
and see Table 15 for details). At power-up, if
DSP
= DV
DD
, the default value of CPHA is zero and if
DSP
= DGND, the default value of CPHA is one. The
default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 16.
To read back the device
’
s CPOL and CPHA bits, use
the command in Table 17.
UPIO Bits (UPSL1, UPSL2, UP0–UP3)
The MAX5290
–
MAX5295 provide two user-programma-
ble input/output (UPIO) ports: UPIO1 and UPIO2. These
ports have 15 possible configurations, as shown in
Table 22. UPIO1 and UPIO2 can be programmed inde-
pendently or simultaneously by writing to the UPSL1,
UPSL2, and UP0
–
UP3 bits (see Table 18).
Table 19 shows how UPIO1 and UPIO2 are selected for
configuration. The UP0
–
UP3 bits select the desired
functions for UPIO1 and/or UPIO2 (see Table 22).
Default states of UP10_ are high impedance. If using
UP10_, connect 10k
pullup resistors from each UPIO
pin to DV
DD
.
UPIO Programming Example:
To set only UPIO1 as
LDAC
and leave UPIO2
unchanged, write the command in Table 20.
The UPIO selection and configuration bits can be read
back from the MAX5290
–
MAX5295 when UPIO1 or
UPIO2 is configured as a DOUTRB output. Table 21
shows the read-back data format for the UPIO bits.
Writing a 1110 101X XXXX XXXX initiates a read operation
of the UPIO bits. The data is clocked out starting on the
9th clock cycle of the sequence. UP3-2 through UP0-2
provide the UP3
–
UP0 configuration bits for UPIO2 (see
Table 22), and UP3-1 through UP0-1 provide the
UP3
–
UP0 configuration bits for UPIO1.
Table 18. UPIO Write Command
DATA
DIN
CONTROL BITS
1
1
DATA BITS
1
0
1
0
0
X
UPSL2 UPSL1
UP3
UP2
UP1
UP0
X
X
X = Don’t care.
Table 19. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2
0
0
1
1
UPSL1
0
1
0
1
UPIO PORT SELECTED
None selected
UPIO1 selected
UPIO2 selected
Both UPIO1 and UPIO2 selected
相關PDF資料
PDF描述
MAX5291AEUE Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
MAX5290AEUD Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
MAX5290BEUD Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
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相關代理商/技術參數(shù)
參數(shù)描述
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MAX5291BEUE+T 功能描述:數(shù)模轉換器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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